^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*-*- linux-c -*-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __I810_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __I810_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/agp_backend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Fence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TILEWALK_X (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TILEWALK_Y (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Raster ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define COLOR_COPY_ROP 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PAT_COPY_ROP 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLEAR_ROP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WHITE_ROP 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INVERT_ROP 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XOR_ROP 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* 2D Engine definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SOLIDPATTERN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NONSOLID 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BPP8 (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BPP16 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BPP24 (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PIXCONF8 (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PIXCONF15 (4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PIXCONF16 (5 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PIXCONF24 (6 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PIXCONF32 (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DYN_COLOR_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DYN_COLOR_DIS (0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define INCREMENT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DECREMENT (0x01 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ARB_ON 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ARB_OFF 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SYNC_FLIP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ASYNC_FLIP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OPTYPE_MASK 0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PARSER_MASK 0x001F8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define D2_MASK 0x001FC000 /* 2D mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Instruction type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* There are more but pertains to 3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PARSER 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BLIT (0x02 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RENDER (0x03 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Parser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NOP 0x00 /* No operation, padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BP_INT (0x01 << 23) /* Breakpoint interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define USR_INT (0x02 << 23) /* User interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WAIT_FOR_EVNT (0x03 << 23) /* Wait for event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FLUSH (0x04 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CONTEXT_SEL (0x05 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REPORT_HEAD (0x07 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ARB_ON_OFF (0x08 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OVERLAY_FLIP (0x11 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LOAD_SCAN_INC (0x12 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LOAD_SCAN_EX (0x13 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FRONT_BUFFER (0x14 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DEST_BUFFER (0x15 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define Z_BUFFER (0x16 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STORE_DWORD_IMM (0x20 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STORE_DWORD_IDX (0x21 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BATCH_BUFFER (0x30 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Blit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SETUP_BLIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SETUP_MONO_PATTERN_SL_BLT (0x10 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PIXEL_BLT (0x20 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SCANLINE_BLT (0x21 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEXT_BLT (0x22 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEXT_IMM_BLT (0x30 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define COLOR_BLT (0x40 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MONO_PAT_BLIT (0x42 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SOURCE_COPY_BLIT (0x43 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MONO_SOURCE_COPY_BLIT (0x44 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SOURCE_COPY_IMMEDIATE (0x60 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MONO_SOURCE_COPY_IMMEDIATE (0x61 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VERSION_MAJOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VERSION_MINOR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VERSION_TEENIE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BRANCH_VERSION ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* mvo: intel i815 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifndef PCI_DEVICE_ID_INTEL_82815_100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCI_DEVICE_ID_INTEL_82815_100 0x1102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCI_DEVICE_ID_INTEL_82815_NOAGP 0x1112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL 0x1130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* General Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define I810_PAGESIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MAX_DMA_SIZE (1024 * 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SAREA_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCI_I810_MISCC 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MMIO_SIZE (512*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GTT_SIZE (16*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RINGBUFFER_SIZE (64*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CURSOR_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MAX_KEY 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define WAIT_COUNT 10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IRING_PAD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FONTDATAMAX 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Masks (AND ops) and OR's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FB_START_MASK (0x3f << (32 - 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MMIO_ADDR_MASK (0x1FFF << (32 - 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FREQ_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SCR_OFF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRAM_ON 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DRAM_OFF 0xE7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PG_ENABLE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RING_SIZE_MASK (RINGBUFFER_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* defines for restoring registers partially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ADDR_MAP_MASK (0x07 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DISP_CTRL ~0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PIXCONF_0 (0x64 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PIXCONF_2 (0xF3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PIXCONF_1 (0xF0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MN_MASK 0x3FF03FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define P_OR (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DAC_BIT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define INTERLACE_BIT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IER_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMR_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DPMS_MASK 0xF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define POWERON 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define STANDBY 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SUSPEND 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define POWERDOWN 0xA0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EMR_MASK ~0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FW_BLC_MASK ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Ringbuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RBUFFER_START_MASK 0xFFFFF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RBUFFER_SIZE_MASK 0x001FF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RBUFFER_HEAD_MASK 0x001FFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RBUFFER_TAIL_MASK 0x001FFFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Video Timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define REF_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TARGET_N_MAX 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MAX_PIXELCLOCK 230000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MIN_PIXELCLOCK 15000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VFMAX 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VFMIN 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HFMAX 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HFMIN 29000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CURSOR_ENABLE_MASK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CURSOR_MODE_64_TRANS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CURSOR_MODE_64_XOR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CURSOR_MODE_64_3C 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define COORD_INACTIVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define COORD_ACTIVE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EXTENDED_PALETTE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* AGP Memory Types*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AGP_NORMAL_MEMORY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AGP_DCACHE_MEMORY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AGP_PHYSICAL_MEMORY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Allocated resource Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FRAMEBUFFER_REQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MMIO_REQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PCI_DEVICE_ENABLED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HAS_FONTCACHE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* driver flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HAS_ACCELERATION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ALWAYS_SYNC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define LOCKUP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct gtt_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct agp_memory *i810_fb_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct agp_memory *i810_cursor_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct mode_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 pixclock, M, N, P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 cr00, cr01, cr02, cr03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 cr04, cr05, cr06, cr07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 cr09, cr10, cr11, cr12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 cr13, cr15, cr16, cr30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 cr31, cr32, cr33, cr35, cr39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 bpp8_100, bpp16_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 bpp24_100, bpp8_133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 bpp16_133, bpp24_133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct heap_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long physical;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __u8 __iomem *virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct state_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 dclk_1d, dclk_2d, dclk_0ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 pixconf, fw_blc, pgtbl_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 fence0, hws_pga, dplystas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 bltcntl, hwstam, ier, iir, imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 cr00, cr01, cr02, cr03, cr04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 cr05, cr06, cr07, cr08, cr09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 cr10, cr11, cr12, cr13, cr14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 cr15, cr16, cr17, cr80, gr10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 cr30, cr31, cr32, cr33, cr35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 cr39, cr41, cr70, sr01, msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct i810fb_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct i810fb_i2c_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct i810fb_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct i2c_algo_bit_data algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned long ddc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct i810fb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct mode_registers regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct state_registers hw_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct gtt_data i810_gtt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct fb_ops i810fb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct heap_data aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct heap_data fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct heap_data iring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct heap_data cursor_heap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct vgastate state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct i810fb_i2c_chan chan[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct mutex open_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int use_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned long mmio_start_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 __iomem *mmio_start_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 pixconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 mem_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 res_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 dev_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 cur_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 blit_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 ovract;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 ddc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u16 bltcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 interlace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Register I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define i810_readb(where, mmio) readb(mmio + where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define i810_readw(where, mmio) readw(mmio + where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define i810_readl(where, mmio) readl(mmio + where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define i810_writeb(where, mmio, val) writeb(val, mmio + where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define i810_writew(where, mmio, val) writew(val, mmio + where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define i810_writel(where, mmio, val) writel(val, mmio + where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif /* __I810_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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