Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) copy of this software and associated documentation files (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) "Software"), to deal in the Software without restriction, including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) without limitation the rights to use, copy, modify, merge, publish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) distribute, sub license, and/or sell copies of the Software, and to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) permit persons to whom the Software is furnished to do so, subject to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) The above copyright notice and this permission notice (including the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) next paragraph) shall be included in all copies or substantial portions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *   Kevin E. Martin <kevin@precisioninsight.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* I/O register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SRX VGA_SEQ_I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GRX VGA_GFX_I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ARX VGA_ATT_IW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define XRX 0x3D6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MRX 0x3D2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* VGA Color Palette Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DACMASK		0x3C6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DACSTATE	0x3C7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DACRX		0x3C7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DACWX		0x3C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DACDATA		0x3C9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* CRT Controller Registers (CRX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define START_ADDR_HI		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define START_ADDR_LO		0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define VERT_SYNC_END		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define EXT_VERT_TOTAL		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define EXT_VERT_DISPLAY	0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define EXT_VERT_SYNC_START	0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define EXT_VERT_BLANK_START	0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define EXT_HORIZ_TOTAL		0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define EXT_HORIZ_BLANK		0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define EXT_START_ADDR		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define EXT_START_ADDR_ENABLE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define EXT_OFFSET		0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define EXT_START_ADDR_HI	0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define INTERLACE_CNTL		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define INTERLACE_ENABLE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define INTERLACE_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Miscellaneous Output Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MSR_R		0x3CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MSR_W		0x3C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IO_ADDR_SELECT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MDA_BASE	0x3B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CGA_BASE	0x3D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* System Configuration Extension Registers (XRX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IO_CTNL		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define EXTENDED_ATTR_CNTL	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define EXTENDED_CRTC_CNTL	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define ADDRESS_MAPPING	0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PACKED_MODE_ENABLE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define LINEAR_MODE_ENABLE	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PAGE_MAPPING_ENABLE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define BITBLT_CNTL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define COLEXP_MODE		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define COLEXP_8BPP		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define COLEXP_16BPP		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define COLEXP_24BPP		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define COLEXP_RESERVED		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CHIP_RESET		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define BITBLT_STATUS		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DISPLAY_CNTL	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define VGA_WRAP_MODE		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define VGA_WRAP_AT_256KB	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define VGA_NO_WRAP		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GUI_MODE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define STANDARD_VGA_MODE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define HIRES_MODE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DRAM_ROW_TYPE	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DRAM_ROW_0		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRAM_ROW_0_SDRAM	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DRAM_ROW_0_EMPTY	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DRAM_ROW_1		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRAM_ROW_1_SDRAM	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRAM_ROW_1_EMPTY	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRAM_ROW_CNTL_LO 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRAM_CAS_LATENCY	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DRAM_RAS_TIMING		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DRAM_RAS_PRECHARGE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRAM_ROW_CNTL_HI 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRAM_EXT_CNTL	0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRAM_REFRESH_RATE	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DRAM_REFRESH_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DRAM_REFRESH_60HZ	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DRAM_REFRESH_FAST_TEST	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRAM_REFRESH_RESERVED	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DRAM_TIMING	0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRAM_ROW_BNDRY_0 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRAM_ROW_BNDRY_1 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DPMS_SYNC_SELECT 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VSYNC_CNTL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VSYNC_ON		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VSYNC_OFF		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HSYNC_CNTL		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HSYNC_ON		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HSYNC_OFF		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PIXPIPE_CONFIG_0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DAC_8_BIT		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DAC_6_BIT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HW_CURSOR_ENABLE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define EXTENDED_PALETTE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PIXPIPE_CONFIG_1 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DISPLAY_COLOR_MODE	0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DISPLAY_VGA_MODE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DISPLAY_8BPP_MODE	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DISPLAY_15BPP_MODE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DISPLAY_16BPP_MODE	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DISPLAY_24BPP_MODE	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DISPLAY_32BPP_MODE	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PIXPIPE_CONFIG_2 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DISPLAY_GAMMA_ENABLE	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DISPLAY_GAMMA_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OVERLAY_GAMMA_ENABLE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OVERLAY_GAMMA_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CURSOR_CONTROL	0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CURSOR_ORIGIN_SCREEN	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CURSOR_ORIGIN_DISPLAY	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CURSOR_MODE		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CURSOR_MODE_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CURSOR_MODE_32_4C_AX	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CURSOR_MODE_128_2C	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CURSOR_MODE_128_1C	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CURSOR_MODE_64_3C	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CURSOR_MODE_64_4C_AX	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CURSOR_MODE_64_4C	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CURSOR_MODE_RESERVED	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CURSOR_BASEADDR_LO 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CURSOR_BASEADDR_HI 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CURSOR_X_LO	0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CURSOR_X_HI	0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CURSOR_X_POS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CURSOR_X_NEG		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CURSOR_Y_LO	0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CURSOR_Y_HI	0xA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CURSOR_Y_POS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CURSOR_Y_NEG		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VCLK2_VCO_M	0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VCLK2_VCO_N	0xC9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VCLK2_VCO_MN_MSBS 0xCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VCO_N_MSBS		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VCO_M_MSBS		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define VCLK2_VCO_DIV_SEL 0xCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define POST_DIV_SELECT		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define POST_DIV_1		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define POST_DIV_2		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define POST_DIV_4		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define POST_DIV_8		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define POST_DIV_16		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define POST_DIV_32		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define VCO_LOOP_DIV_BY_4M	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define VCO_LOOP_DIV_BY_16M	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define REF_CLK_DIV_BY_5	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define REF_DIV_4		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define REF_DIV_1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PLL_CNTL	0xCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PLL_MEMCLK_SEL		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PLL_MEMCLK__66667KHZ	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PLL_MEMCLK__75000KHZ	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PLL_MEMCLK__88889KHZ	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PLL_MEMCLK_100000KHZ	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Multimedia Extension Registers (MRX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ACQ_CNTL_1	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ACQ_CNTL_2	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define FRAME_CAP_MODE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CONT_CAP_MODE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SINGLE_CAP_MODE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ACQ_CNTL_3	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define COL_KEY_CNTL_1		0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BLANK_DISP_OVERLAY	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define LP_FIFO		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HP_FIFO		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define INSTPNT		0x3040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define LP_FIFO_COUNT	0x3040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HP_FIFO_COUNT	0x3041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* FIFO Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLIENT		0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLIENT_2D	0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Command Parser Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define COMPARS		0x3038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TWO_D_INST_DISABLE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define THREE_D_INST_DISABLE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define STATE_VAR_UPDATE_DISABLE	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PAL_STIP_DISABLE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Interrupt Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IER		0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IIR		0x3032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMR		0x3034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ISR		0x3036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define VMIINTB_EVENT		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GPIO4_INT		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DISP_FLIP_EVENT		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DVD_PORT_DMA		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DISP_VBLANK		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define FIFO_EMPTY_DMA_DONE	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define INST_PARSER_ERROR	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define USER_DEFINED		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define BREAKPOINT		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DISP_HORIZ_COUNT	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DISP_VSYNC		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CAPTURE_HORIZ_COUNT	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CAPTURE_VSYNC		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define THREE_D_PIPE_FLUSHED	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* FIFO Watermark and Burst Length Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define FWATER_BLC	0x00006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define LMI_BURST_LENGTH	0x7F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define LMI_FIFO_WATERMARK	0x003F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AGP_BURST_LENGTH	0x00007F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AGP_FIFO_WATERMARK	0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* BitBLT Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SRC_DST_PITCH	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DST_PITCH		0x1FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SRC_PITCH		0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define COLEXP_BG_COLOR	0x00040004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define COLEXP_FG_COLOR	0x00040008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MONO_SRC_CNTL	0x0004000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MONO_USE_COLEXP		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MONO_USE_SRCEXP		0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MONO_DATA_ALIGN		0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MONO_BIT_ALIGN		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MONO_BYTE_ALIGN		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MONO_WORD_ALIGN		0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MONO_DWORD_ALIGN	0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MONO_QWORD_ALIGN	0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MONO_SRC_INIT_DSCRD	0x003F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MONO_SRC_RIGHT_CLIP	0x00003F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MONO_SRC_LEFT_CLIP	0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define BITBLT_CONTROL	0x00040010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define BLTR_STATUS		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DYN_DEPTH		0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DYN_DEPTH_8BPP		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DYN_DEPTH_16BPP		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DYN_DEPTH_24BPP		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DYN_DEPTH_32BPP		0x03000000	/* Unimplemented on the i740 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DYN_DEPTH_ENABLE	0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PAT_VERT_ALIGN		0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SOLID_PAT_SELECT	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PAT_IS_IN_COLOR		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PAT_IS_MONO		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MONO_PAT_TRANSP		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define COLOR_TRANSP_ROP	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define COLOR_TRANSP_DST	0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define COLOR_TRANSP_EQ		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define COLOR_TRANSP_NOT_EQ	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define COLOR_TRANSP_ENABLE	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MONO_SRC_TRANSP		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SRC_IS_IN_COLOR		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SRC_IS_MONO		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SRC_USE_SRC_ADDR	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SRC_USE_BLTDATA		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define BLT_TOP_TO_BOT		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define BLT_BOT_TO_TOP		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define BLT_LEFT_TO_RIGHT	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define BLT_RIGHT_TO_LEFT	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define BLT_ROP			0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define BLT_PAT_ADDR	0x00040014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define BLT_SRC_ADDR	0x00040018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define BLT_DST_ADDR	0x0004001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define BLT_DST_H_W	0x00040020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define BLT_DST_HEIGHT		0x1FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define BLT_DST_WIDTH		0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SRCEXP_BG_COLOR	0x00040024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SRCEXP_FG_COLOR	0x00040028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define BLTDATA		0x00050000