^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Frame buffer device for IBM GXT4500P/6500P and GXT4000P/6000P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * display adaptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 Paul Mackerras, IBM Corp. <paulus@samba.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCI_DEVICE_ID_IBM_GXT4500P 0x21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_DEVICE_ID_IBM_GXT6500P 0x21b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCI_DEVICE_ID_IBM_GXT4000P 0x16e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_DEVICE_ID_IBM_GXT6000P 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* GXT4500P registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Registers in PCI config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CFG_ENDIAN0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Misc control/status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STATUS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CTRL_REG0 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CR0_HALT_DMA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CR0_RASTER_RESET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CR0_GEOM_RESET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CR0_MEM_CTRLER_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Framebuffer control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FB_AB_CTRL 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FB_CD_CTRL 0x1104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FB_WID_CTRL 0x1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FB_Z_CTRL 0x110c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FB_VGA_CTRL 0x1110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REFRESH_AB_CTRL 0x1114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REFRESH_CD_CTRL 0x1118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FB_OVL_CTRL 0x111c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FB_CTRL_TYPE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FB_CTRL_WIDTH_MASK 0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FB_CTRL_WIDTH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FB_CTRL_START_SEG_MASK 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REFRESH_START 0x1098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REFRESH_SIZE 0x109c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* "Direct" framebuffer access registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DFA_FB_A 0x11e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DFA_FB_B 0x11e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DFA_FB_C 0x11e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DFA_FB_D 0x11ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DFA_FB_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DFA_FB_BASE_MASK 0x03f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DFA_FB_STRIDE_1k 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DFA_FB_STRIDE_2k 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DFA_FB_STRIDE_4k 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DFA_PIX_8BIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DFA_PIX_16BIT_565 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DFA_PIX_16BIT_1555 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DFA_PIX_24BIT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DFA_PIX_32BIT 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* maps DFA_PIX_* to pixel size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const unsigned char pixsize[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 1, 2, 2, 2, 4, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Display timing generator registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DTG_CONTROL 0x1900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DTG_CTL_SCREEN_REFRESH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DTG_CTL_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DTG_HORIZ_EXTENT 0x1904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DTG_HORIZ_DISPLAY 0x1908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DTG_HSYNC_START 0x190c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DTG_HSYNC_END 0x1910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DTG_HSYNC_END_COMP 0x1914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DTG_VERT_EXTENT 0x1918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DTG_VERT_DISPLAY 0x191c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DTG_VSYNC_START 0x1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DTG_VSYNC_END 0x1924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DTG_VERT_SHORT 0x1928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* PLL/RAMDAC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DISP_CTL 0x402c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DISP_CTL_OFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SYNC_CTL 0x4034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SYNC_CTL_SYNC_ON_RGB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SYNC_CTL_SYNC_OFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SYNC_CTL_HSYNC_INV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SYNC_CTL_VSYNC_INV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SYNC_CTL_HSYNC_OFF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SYNC_CTL_VSYNC_OFF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PLL_M 0x4040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLL_N 0x4044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PLL_POSTDIV 0x4048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PLL_C 0x404c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Hardware cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CURSOR_X 0x4078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CURSOR_Y 0x407c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CURSOR_HOTSPOT 0x4080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CURSOR_MODE 0x4084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CURSOR_MODE_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CURSOR_MODE_4BPP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CURSOR_PIXMAP 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CURSOR_CMAP 0x7400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Window attribute table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WAT_FMT 0x4100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WAT_FMT_24BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WAT_FMT_16BIT_565 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WAT_FMT_16BIT_1555 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WAT_FMT_32BIT 3 /* 0 vs. 3 is a guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WAT_FMT_8BIT_332 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WAT_FMT_8BIT 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define WAT_FMT_NO_CMAP 4 /* ORd in to other values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WAT_CMAP_OFFSET 0x4104 /* 4-bit value gets << 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define WAT_CTRL 0x4108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define WAT_CTRL_SEL_B 1 /* select B buffer if 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define WAT_CTRL_NO_INC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define WAT_GAMMA_CTRL 0x410c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define WAT_GAMMA_DISABLE 1 /* disables gamma cmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define WAT_OVL_CTRL 0x430c /* controls overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Indexed by DFA_PIX_* values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const unsigned char watfmt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) WAT_FMT_8BIT, WAT_FMT_16BIT_565, WAT_FMT_16BIT_1555, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) WAT_FMT_24BIT, WAT_FMT_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Colormap array; 1k entries of 4 bytes each */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CMAP 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define readreg(par, reg) readl((par)->regs + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define writereg(par, reg, val) writel((val), (par)->regs + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct gxt4500_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int pixfmt; /* pixel format, see DFA_PIX_* values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* PLL parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int refclk_ps; /* ref clock period in picoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int pll_m; /* ref clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int pll_n; /* VCO divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int pll_pd1; /* first post-divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int pll_pd2; /* second post-divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 pseudo_palette[16]; /* used in color blits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* mode requested by user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static char *mode_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* default mode: 1280x1024 @ 60 Hz, 8 bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct fb_videomode defaultmode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .xres = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .yres = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .pixclock = 9295,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .left_margin = 248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .right_margin = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .upper_margin = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .lower_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .hsync_len = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* List of supported cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) enum gxt_cards {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) GXT4500P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) GXT6500P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GXT4000P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GXT6000P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Card-specific information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct cardinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int refclk_ps; /* period of PLL reference clock in ps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const char *cardname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } cardinfo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [GXT4500P] = { .refclk_ps = 9259, .cardname = "IBM GXT4500P" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [GXT6500P] = { .refclk_ps = 9259, .cardname = "IBM GXT6500P" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [GXT4000P] = { .refclk_ps = 40000, .cardname = "IBM GXT4000P" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [GXT6000P] = { .refclk_ps = 40000, .cardname = "IBM GXT6000P" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * The refclk and VCO dividers appear to use a linear feedback shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * register, which gets reloaded when it reaches a terminal value, at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * which point the divider output is toggled. Thus one can obtain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * whatever divisor is required by putting the appropriate value into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * the reload register. For a divisor of N, one puts the value from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * the LFSR sequence that comes N-1 places before the terminal value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * into the reload register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned char mdivtab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* 1 */ 0x3f, 0x00, 0x20, 0x10, 0x28, 0x14, 0x2a, 0x15, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* 10 */ 0x25, 0x32, 0x19, 0x0c, 0x26, 0x13, 0x09, 0x04, 0x22, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* 20 */ 0x08, 0x24, 0x12, 0x29, 0x34, 0x1a, 0x2d, 0x36, 0x1b, 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* 30 */ 0x06, 0x23, 0x31, 0x38, 0x1c, 0x2e, 0x17, 0x0b, 0x05, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* 40 */ 0x21, 0x30, 0x18, 0x2c, 0x16, 0x2b, 0x35, 0x3a, 0x1d, 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* 50 */ 0x27, 0x33, 0x39, 0x3c, 0x1e, 0x2f, 0x37, 0x3b, 0x3d, 0x3e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* 60 */ 0x1f, 0x0f, 0x07, 0x03, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const unsigned char ndivtab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* 2 */ 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x78, 0xbc, 0x5e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* 10 */ 0x2f, 0x17, 0x0b, 0x85, 0xc2, 0xe1, 0x70, 0x38, 0x9c, 0x4e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* 20 */ 0xa7, 0xd3, 0xe9, 0xf4, 0xfa, 0xfd, 0xfe, 0x7f, 0xbf, 0xdf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* 30 */ 0xef, 0x77, 0x3b, 0x1d, 0x8e, 0xc7, 0xe3, 0x71, 0xb8, 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* 40 */ 0x6e, 0xb7, 0x5b, 0x2d, 0x16, 0x8b, 0xc5, 0xe2, 0xf1, 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* 50 */ 0xfc, 0x7e, 0x3f, 0x9f, 0xcf, 0x67, 0xb3, 0xd9, 0x6c, 0xb6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* 60 */ 0xdb, 0x6d, 0x36, 0x9b, 0x4d, 0x26, 0x13, 0x89, 0xc4, 0x62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* 70 */ 0xb1, 0xd8, 0xec, 0xf6, 0xfb, 0x7d, 0xbe, 0x5f, 0xaf, 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* 80 */ 0x2b, 0x95, 0x4a, 0x25, 0x92, 0x49, 0xa4, 0x52, 0x29, 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* 90 */ 0xca, 0x65, 0xb2, 0x59, 0x2c, 0x96, 0xcb, 0xe5, 0xf2, 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* 100 */ 0x3c, 0x1e, 0x0f, 0x07, 0x83, 0x41, 0x20, 0x90, 0x48, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* 110 */ 0x12, 0x09, 0x84, 0x42, 0xa1, 0x50, 0x28, 0x14, 0x8a, 0x45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* 120 */ 0xa2, 0xd1, 0xe8, 0x74, 0xba, 0xdd, 0xee, 0xf7, 0x7b, 0x3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* 130 */ 0x9e, 0x4f, 0x27, 0x93, 0xc9, 0xe4, 0x72, 0x39, 0x1c, 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* 140 */ 0x87, 0xc3, 0x61, 0x30, 0x18, 0x8c, 0xc6, 0x63, 0x31, 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* 150 */ 0xcc, 0xe6, 0x73, 0xb9, 0x5c, 0x2e, 0x97, 0x4b, 0xa5, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* 160 */ 0x69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int calc_pll(int period_ps, struct gxt4500_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int m, n, pdiv1, pdiv2, postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int pll_period, best_error, t, intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* only deal with range 5MHz - 300MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (period_ps < 3333 || period_ps > 200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) best_error = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (pdiv1 = 1; pdiv1 <= 8; ++pdiv1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (pdiv2 = 1; pdiv2 <= pdiv1; ++pdiv2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) postdiv = pdiv1 * pdiv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pll_period = DIV_ROUND_UP(period_ps, postdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* keep pll in range 350..600 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (pll_period < 1666 || pll_period > 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (m = 1; m <= 64; ++m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) intf = m * par->refclk_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (intf > 500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) n = intf * postdiv / period_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (n < 3 || n > 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) t = par->refclk_ps * m * postdiv / n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) t -= period_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (t >= 0 && t < best_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) par->pll_m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) par->pll_n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) par->pll_pd1 = pdiv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) par->pll_pd2 = pdiv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) best_error = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (best_error == 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int calc_pixclock(struct gxt4500_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return par->refclk_ps * par->pll_m * par->pll_pd1 * par->pll_pd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) / par->pll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int gxt4500_var_to_par(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct gxt4500_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (var->xres + var->xoffset > var->xres_virtual ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) var->yres + var->yoffset > var->yres_virtual ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) var->xres_virtual > 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (calc_pll(var->pixclock, par) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (var->bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (var->transp.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) par->pixfmt = DFA_PIX_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) par->pixfmt = DFA_PIX_24BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) par->pixfmt = DFA_PIX_24BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (var->green.length == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) par->pixfmt = DFA_PIX_16BIT_1555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) par->pixfmt = DFA_PIX_16BIT_565;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) par->pixfmt = DFA_PIX_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct fb_bitfield eightbits = {0, 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct fb_bitfield nobits = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void gxt4500_unpack_pixfmt(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int pixfmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) var->bits_per_pixel = pixsize[pixfmt] * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) var->red = eightbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) var->green = eightbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) var->blue = eightbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) var->transp = nobits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) switch (pixfmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case DFA_PIX_16BIT_565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) var->red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) var->green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case DFA_PIX_16BIT_1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) var->red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) var->green.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) var->transp.length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case DFA_PIX_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) var->transp.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (pixfmt != DFA_PIX_8BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) var->green.offset = var->blue.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) var->red.offset = var->green.offset + var->green.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (var->transp.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) var->transp.offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) var->red.offset + var->red.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int gxt4500_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct gxt4500_par par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) par = *(struct gxt4500_par *)info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) err = gxt4500_var_to_par(var, &par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) var->pixclock = calc_pixclock(&par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) gxt4500_unpack_pixfmt(var, par.pixfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int gxt4500_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct gxt4500_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 ctrlreg, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int dfa_ctl, pixfmt, stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int wid_tiles, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int prefetch_pix, htot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct gxt4500_par save_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) save_par = *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) err = gxt4500_var_to_par(var, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *par = save_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* turn off DTG for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ctrlreg = readreg(par, DTG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ctrlreg &= ~(DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) writereg(par, DTG_CONTROL, ctrlreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* set PLL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tmp = readreg(par, PLL_C) & ~0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (par->pll_n < 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tmp |= 0x29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (par->pll_n < 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tmp |= 0x35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) else if (par->pll_n < 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tmp |= 0x76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tmp |= 0x7e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writereg(par, PLL_C, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writereg(par, PLL_M, mdivtab[par->pll_m - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writereg(par, PLL_N, ndivtab[par->pll_n - 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) tmp = ((8 - par->pll_pd2) << 3) | (8 - par->pll_pd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (par->pll_pd1 == 8 || par->pll_pd2 == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* work around erratum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writereg(par, PLL_POSTDIV, tmp | 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) writereg(par, PLL_POSTDIV, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* turn off hardware cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writereg(par, CURSOR_MODE, CURSOR_MODE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* reset raster engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* set display timing generator registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) htot = var->xres + var->left_margin + var->right_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) var->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writereg(par, DTG_HORIZ_EXTENT, htot - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) writereg(par, DTG_HSYNC_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) var->xres + var->right_margin + var->hsync_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writereg(par, DTG_HSYNC_END_COMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) var->xres + var->right_margin + var->hsync_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) writereg(par, DTG_VERT_EXTENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) var->yres + var->upper_margin + var->lower_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) var->vsync_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) writereg(par, DTG_VERT_DISPLAY, var->yres - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writereg(par, DTG_VSYNC_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) var->yres + var->lower_margin + var->vsync_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) prefetch_pix = 3300000 / var->pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (prefetch_pix >= htot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) prefetch_pix = htot - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writereg(par, DTG_CONTROL, ctrlreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* calculate stride in DFA aperture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (var->xres_virtual > 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) stride = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dfa_ctl = DFA_FB_STRIDE_4k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } else if (var->xres_virtual > 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) stride = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dfa_ctl = DFA_FB_STRIDE_2k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) stride = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dfa_ctl = DFA_FB_STRIDE_1k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Set up framebuffer definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) wid_tiles = (var->xres_virtual + 63) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* XXX add proper FB allocation here someday */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Set up framebuffer access by CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pixfmt = par->pixfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dfa_ctl |= DFA_FB_ENABLE | pixfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writereg(par, DFA_FB_A, dfa_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Set up window attribute table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * We set all WAT entries the same so it doesn't matter what the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * window ID (WID) plane contains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for (i = 0; i < 32; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) writereg(par, WAT_CMAP_OFFSET + (i << 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writereg(par, WAT_CTRL + (i << 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Set sync polarity etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ctrlreg = readreg(par, SYNC_CTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ~(SYNC_CTL_SYNC_ON_RGB | SYNC_CTL_HSYNC_INV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SYNC_CTL_VSYNC_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (var->sync & FB_SYNC_ON_GREEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ctrlreg |= SYNC_CTL_SYNC_ON_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ctrlreg |= SYNC_CTL_HSYNC_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ctrlreg |= SYNC_CTL_VSYNC_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) writereg(par, SYNC_CTL, ctrlreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) info->fix.line_length = stride * pixsize[pixfmt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) info->fix.visual = (pixfmt == DFA_PIX_8BIT)? FB_VISUAL_PSEUDOCOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) FB_VISUAL_DIRECTCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int gxt4500_setcolreg(unsigned int reg, unsigned int red,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned int green, unsigned int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 cmap_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct gxt4500_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (reg > 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cmap_entry = ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) (green & 0xff00) | (blue >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) writereg(par, CMAP + reg * 4, cmap_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 *pal = info->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 val = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) switch (par->pixfmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case DFA_PIX_16BIT_565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) val |= (reg << 11) | (reg << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case DFA_PIX_16BIT_1555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val |= (reg << 10) | (reg << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case DFA_PIX_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val |= (reg << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case DFA_PIX_24BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) val |= (reg << 16) | (reg << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pal[reg] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int gxt4500_pan_display(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct gxt4500_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (var->xoffset & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (var->xoffset + info->var.xres > info->var.xres_virtual ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) var->yoffset + info->var.yres > info->var.yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int gxt4500_blank(int blank, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct gxt4500_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int ctrl, dctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ctrl = readreg(par, SYNC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ctrl &= ~(SYNC_CTL_SYNC_OFF | SYNC_CTL_HSYNC_OFF | SYNC_CTL_VSYNC_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dctl = readreg(par, DISP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dctl |= DISP_CTL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) switch (blank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case FB_BLANK_UNBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dctl &= ~DISP_CTL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case FB_BLANK_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ctrl |= SYNC_CTL_SYNC_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case FB_BLANK_HSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ctrl |= SYNC_CTL_HSYNC_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case FB_BLANK_VSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ctrl |= SYNC_CTL_VSYNC_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) default: ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) writereg(par, SYNC_CTL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) writereg(par, DISP_CTL, dctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct fb_fix_screeninfo gxt4500_fix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .id = "IBM GXT4500P",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .visual = FB_VISUAL_PSEUDOCOLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .xpanstep = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .ypanstep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .mmio_len = 0x20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const struct fb_ops gxt4500_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .fb_check_var = gxt4500_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .fb_set_par = gxt4500_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .fb_setcolreg = gxt4500_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .fb_pan_display = gxt4500_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .fb_blank = gxt4500_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* PCI functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int gxt4500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned long reg_phys, fb_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct gxt4500_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct fb_var_screeninfo var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) enum gxt_cards cardtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(&pdev->dev, "gxt4500: cannot enable PCI device: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) reg_phys = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "gxt4500 regs")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_err(&pdev->dev, "gxt4500: cannot get registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto err_nodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) fb_phys = pci_resource_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!request_mem_region(fb_phys, pci_resource_len(pdev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "gxt4500 FB")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_err(&pdev->dev, "gxt4500: cannot get framebuffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) goto err_free_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) info = framebuffer_alloc(sizeof(struct gxt4500_par), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto err_free_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) cardtype = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) par->refclk_ps = cardinfo[cardtype].refclk_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) info->fix = gxt4500_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) strlcpy(info->fix.id, cardinfo[cardtype].cardname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) sizeof(info->fix.id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) info->pseudo_palette = par->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) info->fix.mmio_start = reg_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) par->regs = pci_ioremap_bar(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!par->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_err(&pdev->dev, "gxt4500: cannot map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto err_free_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) info->fix.smem_start = fb_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) info->fix.smem_len = pci_resource_len(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) info->screen_base = pci_ioremap_wc_bar(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(&pdev->dev, "gxt4500: cannot map framebuffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) goto err_unmap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pci_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Set byte-swapping for DFA aperture for all pixel sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* not sure what this means but fgl23 driver does that */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pci_write_config_dword(pdev, CFG_ENDIAN0, 0x2300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* pci_write_config_dword(pdev, CFG_ENDIAN0 + 4, 0x400000);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pci_write_config_dword(pdev, CFG_ENDIAN0 + 8, 0x98530000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) info->fbops = &gxt4500_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) info->flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_XPAN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) err = fb_alloc_cmap(&info->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev_err(&pdev->dev, "gxt4500: cannot allocate cmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) goto err_unmap_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) gxt4500_blank(FB_BLANK_UNBLANK, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(&pdev->dev, "gxt4500: cannot find valid video mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) goto err_free_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) info->var = var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (gxt4500_set_par(info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) printk(KERN_ERR "gxt4500: cannot set video mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto err_free_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (register_framebuffer(info) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) goto err_free_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) fb_info(info, "%s frame buffer device\n", info->fix.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) err_free_cmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) err_unmap_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) err_unmap_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) iounmap(par->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) err_free_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) err_free_fb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) release_mem_region(fb_phys, pci_resource_len(pdev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) err_free_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) release_mem_region(reg_phys, pci_resource_len(pdev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) err_nodev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static void gxt4500_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct fb_info *info = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct gxt4500_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) arch_phys_wc_del(par->wc_cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) iounmap(par->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) release_mem_region(pci_resource_start(pdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) pci_resource_len(pdev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) release_mem_region(pci_resource_start(pdev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pci_resource_len(pdev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* supported chipsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const struct pci_device_id gxt4500_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4500P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .driver_data = GXT4500P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6500P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .driver_data = GXT6500P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4000P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .driver_data = GXT4000P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6000P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .driver_data = GXT6000P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static struct pci_driver gxt4500_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .name = "gxt4500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .id_table = gxt4500_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .probe = gxt4500_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .remove = gxt4500_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int gxt4500_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (fb_get_options("gxt4500", &mode_option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return pci_register_driver(&gxt4500_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) module_init(gxt4500_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void __exit gxt4500_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) pci_unregister_driver(&gxt4500_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) module_exit(gxt4500_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) MODULE_DESCRIPTION("FBDev driver for IBM GXT4500P/6500P and GXT4000P/6000P");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) module_param(mode_option, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\"");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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