^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Geode LX framebuffer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Andres Salomon <dilinger@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _LXFB_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _LXFB_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GP_REG_COUNT (0x7c / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DC_REG_COUNT (0xf0 / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VP_REG_COUNT (0x158 / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FP_REG_COUNT (0x60 / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DC_PAL_COUNT 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DC_HFILT_COUNT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DC_VFILT_COUNT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VP_COEFF_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VP_PAL_COUNT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OUTPUT_CRT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OUTPUT_PANEL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct lxfb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *gp_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *dc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *vp_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int powered_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* register state, for power mgmt functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) uint64_t padsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) uint64_t dotpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) uint64_t dfglcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) uint64_t dcspare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) } msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) uint32_t gp[GP_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) uint32_t dc[DC_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) uint64_t vp[VP_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) uint64_t fp[FP_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) uint32_t dc_pal[DC_PAL_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) uint32_t vp_pal[VP_PAL_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) uint32_t hcoeff[DC_HFILT_COUNT * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) uint32_t vcoeff[DC_VFILT_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) uint32_t vp_coeff[VP_COEFF_SIZE / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return (((xres * (bpp >> 3)) + 7) & ~7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void lx_set_mode(struct fb_info *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int lx_framebuffer_size(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int lx_blank_display(struct fb_info *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int lx_powerdown(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int lx_powerup(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Graphics Processor registers (table 6-29 from the data book) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum gp_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GP_DST_OFFSET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GP_SRC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GP_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GP_WID_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GP_SRC_COLOR_FG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GP_SRC_COLOR_BG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GP_PAT_COLOR_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GP_PAT_COLOR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) GP_PAT_COLOR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GP_PAT_COLOR_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GP_PAT_COLOR_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GP_PAT_COLOR_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GP_PAT_DATA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GP_PAT_DATA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GP_RASTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GP_VECTOR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GP_BLT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GP_BLT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GP_HST_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) GP_BASE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) GP_CMD_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) GP_CMD_BOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) GP_CMD_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) GP_CMD_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GP_CH3_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) GP_CH3_MODE_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GP_CH3_WIDHI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) GP_CH3_HSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GP_LUT_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GP_LUT_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GP_INT_CNTRL, /* 0x78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GP_BLT_STATUS_CE (1 << 4) /* cmd buf empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GP_BLT_STATUS_PB (1 << 0) /* primitive busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Display Controller registers (table 6-47 from the data book) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum dc_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DC_UNLOCK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DC_GENERAL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DC_DISPLAY_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DC_ARB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DC_FB_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DC_CB_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DC_CURS_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DC_RSVD_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DC_VID_Y_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DC_VID_U_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DC_VID_V_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DC_DV_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DC_LINE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DC_GFX_PITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DC_VID_YUV_PITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DC_RSVD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DC_H_ACTIVE_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DC_H_BLANK_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DC_H_SYNC_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DC_RSVD_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DC_V_ACTIVE_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DC_V_BLANK_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DC_V_SYNC_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DC_FB_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DC_CURSOR_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DC_CURSOR_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DC_RSVD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DC_LINE_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DC_PAL_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DC_PAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DC_DFIFO_DIAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DC_CFIFO_DIAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DC_VID_DS_DELTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DC_GLIU0_MEM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DC_DV_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DC_DV_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DC_GFX_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DC_IRQ_FILT_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DC_FILT_COEFF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DC_FILT_COEFF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DC_VBI_EVEN_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DC_VBI_ODD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DC_VBI_HOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DC_VBI_LN_ODD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DC_VBI_LN_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DC_VBI_PITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DC_CLR_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DC_CLR_KEY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DC_CLR_KEY_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DC_CLR_KEY_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DC_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DC_RSVD_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DC_RSVD_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DC_GENLK_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DC_VID_EVEN_Y_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DC_VID_EVEN_U_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DC_VID_EVEN_V_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DC_V_ACTIVE_EVEN_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DC_V_BLANK_EVEN_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DC_V_SYNC_EVEN_TIMING, /* 0xec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DC_UNLOCK_LOCK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DC_GENERAL_CFG_FDTY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DC_GENERAL_CFG_VGAE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DC_GENERAL_CFG_DECE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DC_GENERAL_CFG_CMPE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DC_GENERAL_CFG_VIDE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DC_GENERAL_CFG_DFLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DC_DISPLAY_CFG_VISL (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DC_DISPLAY_CFG_PALB (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DC_DISPLAY_CFG_DCEN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DC_DISPLAY_CFG_TRUP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DC_DISPLAY_CFG_VDEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DC_DISPLAY_CFG_GDEN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DC_DISPLAY_CFG_TGEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DC_DV_TOP_DV_TOP_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) | (1 << 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DC_DV_CTL_DV_LINE_SIZE_1K (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) | (1 << 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DC_DV_CTL_CLEAR_DV_RAM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DC_IRQ_FILT_CTL_H_FILT_SEL (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21) /* undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DC_IRQ_STATUS (1 << 20) /* undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DC_IRQ_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DC_GENLK_CTL_FLICK_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DC_GENLK_CTL_GENLK_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Video Processor registers (table 6-71).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * There is space for 64 bit values, but we never use more than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * lower 32 bits. The actual register save/restore code only bothers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * to restore those 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum vp_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) VP_VCFG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) VP_DCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) VP_VX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) VP_VY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) VP_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) VP_VCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) VP_VCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) VP_PAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) VP_PDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) VP_SLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) VP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) VP_CCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) VP_VYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) VP_VXS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) VP_RSVD_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) VP_VDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) VP_RSVD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) VP_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) VP_CRC32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) VP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) VP_CCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) VP_CCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) VP_CC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) VP_CC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) VP_A1X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) VP_A1Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) VP_A1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) VP_A1T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) VP_A2X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) VP_A2Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) VP_A2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) VP_A2T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) VP_A3X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) VP_A3Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) VP_A3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) VP_A3T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) VP_VRR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) VP_AWT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) VP_VTM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) VP_VYE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) VP_A1YE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) VP_A2YE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) VP_A3YE, /* 0x150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define VP_VCFG_VID_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define VP_DCFG_GV_GAM (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) | (1 << 18) | (1 << 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define VP_DCFG_CRT_VSYNC_POL (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define VP_DCFG_CRT_HSYNC_POL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define VP_DCFG_DAC_BL_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define VP_DCFG_VSYNC_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define VP_DCFG_HSYNC_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define VP_DCFG_CRT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define VP_MISC_APWRDN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define VP_MISC_DACPWRDN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define VP_MISC_BYP_BOTH (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Flat Panel registers (table 6-71).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Also 64 bit registers; see above note about 32-bit handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* we're actually in the VP register space, starting at address 0x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define VP_FP_START 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum fp_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FP_PT1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) FP_PT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) FP_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) FP_DFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) FP_RSVD_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) FP_RSVD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) FP_RSVD_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) FP_RSVD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) FP_RSVD_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) FP_DCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) FP_DMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) FP_CRC, /* 0x458 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define FP_PT2_HSP (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define FP_PT2_VSP (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define FP_PT2_SCRC (1 << 27) /* shfclk free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define FP_PM_P (1 << 24) /* panel power ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define FP_PM_PANEL_OFF (1 << 1) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define FP_PM_PANEL_ON (1 << 0) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define FP_DFC_BC ((1 << 4) | (1 << 5) | (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* register access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline uint32_t read_gp(struct lxfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return readl(par->gp_regs + 4*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(val, par->gp_regs + 4*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline uint32_t read_dc(struct lxfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return readl(par->dc_regs + 4*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) writel(val, par->dc_regs + 4*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static inline uint32_t read_vp(struct lxfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return readl(par->vp_regs + 8*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel(val, par->vp_regs + 8*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static inline uint32_t read_fp(struct lxfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return readl(par->vp_regs + 8*reg + VP_FP_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) writel(val, par->vp_regs + 8*reg + VP_FP_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* MSRs are defined in linux/cs5535.h; their bitfields are here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* note: this is actually the VP's GLD_MSR_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP *and* CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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