Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Geode GX2 header information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _GXFB_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _GXFB_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define GP_REG_COUNT   (0x50 / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define DC_REG_COUNT   (0x90 / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define VP_REG_COUNT   (0x138 / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define FP_REG_COUNT   (0x68 / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DC_PAL_COUNT   0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct gxfb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	int enable_crt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	void __iomem *dc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	void __iomem *vid_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	void __iomem *gp_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	int powered_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	/* register state, for power management functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		uint64_t padsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		uint64_t dotpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	} msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	uint32_t gp[GP_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	uint32_t dc[DC_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	uint64_t vp[VP_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	uint64_t fp[FP_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	uint32_t pal[DC_PAL_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) unsigned int gx_frame_buffer_size(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) int gx_line_delta(int xres, int bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) void gx_set_mode(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		unsigned red, unsigned green, unsigned blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) void gx_set_dclk_frequency(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) void gx_configure_display(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) int gx_blank_display(struct fb_info *info, int blank_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) int gx_powerdown(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) int gx_powerup(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Graphics Processor registers (table 6-23 from the data book) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) enum gp_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	GP_DST_OFFSET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	GP_SRC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	GP_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	GP_WID_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	GP_SRC_COLOR_FG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	GP_SRC_COLOR_BG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	GP_PAT_COLOR_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	GP_PAT_COLOR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	GP_PAT_COLOR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	GP_PAT_COLOR_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	GP_PAT_COLOR_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	GP_PAT_COLOR_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	GP_PAT_DATA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	GP_PAT_DATA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	GP_RASTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	GP_VECTOR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	GP_BLT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	GP_BLT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	GP_HST_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	GP_BASE_OFFSET, /* 0x4c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GP_BLT_STATUS_BLT_PENDING	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define GP_BLT_STATUS_BLT_BUSY		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Display Controller registers (table 6-38 from the data book) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) enum dc_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	DC_UNLOCK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	DC_GENERAL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	DC_DISPLAY_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	DC_RSVD_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	DC_FB_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	DC_CB_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	DC_CURS_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	DC_ICON_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	DC_VID_Y_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	DC_VID_U_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	DC_VID_V_ST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	DC_RSVD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	DC_LINE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	DC_GFX_PITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	DC_VID_YUV_PITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	DC_RSVD_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	DC_H_ACTIVE_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	DC_H_BLANK_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	DC_H_SYNC_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	DC_RSVD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	DC_V_ACTIVE_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	DC_V_BLANK_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	DC_V_SYNC_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	DC_RSVD_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	DC_CURSOR_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	DC_CURSOR_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	DC_ICON_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	DC_LINE_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	DC_PAL_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	DC_PAL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	DC_DFIFO_DIAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	DC_CFIFO_DIAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	DC_VID_DS_DELTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	DC_GLIU0_MEM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	DC_RSVD_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	DC_DV_ACC, /* 0x8c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DC_UNLOCK_LOCK			0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DC_UNLOCK_UNLOCK		0x00004758	/* magic value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DC_GENERAL_CFG_YUVM		(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DC_GENERAL_CFG_VDSE		(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DC_GENERAL_CFG_DFHPEL_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DC_GENERAL_CFG_DFHPSL_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DC_GENERAL_CFG_DECE		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DC_GENERAL_CFG_CMPE		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DC_GENERAL_CFG_VIDE		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DC_GENERAL_CFG_ICNE		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DC_GENERAL_CFG_CURE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DC_GENERAL_CFG_DFLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DC_DISPLAY_CFG_A20M		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DC_DISPLAY_CFG_A18M		(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DC_DISPLAY_CFG_PALB		(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DC_DISPLAY_CFG_DISP_MODE_24BPP	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DC_DISPLAY_CFG_DISP_MODE_16BPP	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DC_DISPLAY_CFG_DISP_MODE_8BPP	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DC_DISPLAY_CFG_VDEN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DC_DISPLAY_CFG_GDEN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DC_DISPLAY_CFG_TGEN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * Video Processor registers (table 6-54).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * There is space for 64 bit values, but we never use more than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * lower 32 bits.  The actual register save/restore code only bothers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * to restore those 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum vp_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	VP_VCFG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	VP_DCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	VP_VX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	VP_VY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	VP_VS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	VP_VCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	VP_VCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	VP_GAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	VP_GDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	VP_RSVD_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	VP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	VP_CCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	VP_RSVD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	VP_RSVD_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	VP_RSVD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	VP_VDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	VP_VCO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	VP_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	VP_CRC32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	VP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	VP_CCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	VP_CCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	VP_CC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	VP_CC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	VP_A1X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	VP_A1Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	VP_A1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	VP_A1T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	VP_A2X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	VP_A2Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	VP_A2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	VP_A2T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	VP_A3X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	VP_A3Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	VP_A3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	VP_A3T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	VP_VRR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	VP_AWT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	VP_VTM, /* 0x130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define VP_VCFG_VID_EN			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define VP_DCFG_DAC_VREF		(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define VP_DCFG_GV_GAM			(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define VP_DCFG_VG_CK			(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define VP_DCFG_CRT_SYNC_SKW_DEFAULT	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define VP_DCFG_CRT_SYNC_SKW		((1 << 14) | (1 << 15) | (1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define VP_DCFG_CRT_VSYNC_POL		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define VP_DCFG_CRT_HSYNC_POL		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define VP_DCFG_FP_DATA_EN		(1 << 7)	/* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define VP_DCFG_FP_PWR_EN		(1 << 6)	/* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define VP_DCFG_DAC_BL_EN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define VP_DCFG_VSYNC_EN		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define VP_DCFG_HSYNC_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define VP_DCFG_CRT_EN			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define VP_MISC_GAM_EN			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define VP_MISC_DACPWRDN		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define VP_MISC_APWRDN			(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  * Flat Panel registers (table 6-55).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * Also 64 bit registers; see above note about 32-bit handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* we're actually in the VP register space, starting at address 0x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VP_FP_START		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum fp_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	FP_PT1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	FP_PT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	FP_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	FP_DFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	FP_BLFSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	FP_RLFSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	FP_FMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	FP_FMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	FP_RSVD_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	FP_DCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	FP_DMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	FP_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	FP_FBB, /* 0x460 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define FP_PT1_VSIZE_SHIFT		16		/* undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FP_PT1_VSIZE_MASK		0x7FF0000	/* undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define FP_PT2_HSP			(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define FP_PT2_VSP			(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define FP_PM_P				(1 << 24)       /* panel power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define FP_PM_PANEL_PWR_UP		(1 << 3)        /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define FP_PM_PANEL_PWR_DOWN		(1 << 2)        /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define FP_PM_PANEL_OFF			(1 << 1)        /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define FP_PM_PANEL_ON			(1 << 0)        /* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define FP_DFC_NFI			((1 << 4) | (1 << 5) | (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* register access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static inline uint32_t read_gp(struct gxfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return readl(par->gp_regs + 4*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	writel(val, par->gp_regs + 4*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline uint32_t read_dc(struct gxfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return readl(par->dc_regs + 4*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	writel(val, par->dc_regs + 4*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static inline uint32_t read_vp(struct gxfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return readl(par->vid_regs + 8*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	writel(val, par->vid_regs + 8*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static inline uint32_t read_fp(struct gxfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	return readl(par->vid_regs + 8*reg + VP_FP_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	writel(val, par->vid_regs + 8*reg + VP_FP_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* MSRs are defined in linux/cs5535.h; their bitfields are here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MSR_GLCP_DOTPLL_LOCK		(1 << 25)	/* r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MSR_GLCP_DOTPLL_BYPASS		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MSR_GLCP_DOTPLL_DOTRESET	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MSR_GX_MSR_PADSEL_MASK		0x3FFFFFFF	/* undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MSR_GX_MSR_PADSEL_TFT		0x1FFFFFFF	/* undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MSR_GX_GLD_MSR_CONFIG_FP	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif