^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Freescale DIU Frame Buffer device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Widmer <paul.widmer@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * York Sun <yorksun@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/fsl-diu-fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "edid.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NUM_AOIS 5 /* 1 for plane 0, 2 for planes 1 & 2 each */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* HW cursor parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX_CURS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* INT_STATUS/INT_MASK field descriptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define INT_VSYNC 0x01 /* Vsync interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define INT_UNDRUN 0x04 /* Under run exception interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define INT_PARERR 0x08 /* Display parameters error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * List of supported video modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The first entry is the default video mode. The remain entries are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * order if increasing resolution and frequency. The 320x240-60 mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * the initial AOI for the second and third planes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct fb_videomode fsl_diu_mode_db[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .xres = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .yres = 768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .pixclock = 15385,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .left_margin = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .right_margin = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .upper_margin = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .lower_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .hsync_len = 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .vsync_len = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .xres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .yres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .pixclock = 79440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .left_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .right_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .upper_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .lower_margin = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .hsync_len = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .vsync_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .pixclock = 39722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .left_margin = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .right_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .upper_margin = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .lower_margin = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .hsync_len = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .vsync_len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .refresh = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .pixclock = 32052,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .left_margin = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .right_margin = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .upper_margin = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .lower_margin = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .hsync_len = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .refresh = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .pixclock = 31747,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .left_margin = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .right_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .upper_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .lower_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .hsync_len = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .refresh = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .pixclock = 25057,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .left_margin = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .right_margin = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .upper_margin = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .lower_margin = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .hsync_len = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .vsync_len = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .refresh = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .pixclock = 22272,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .left_margin = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .right_margin = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .upper_margin = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .lower_margin = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .hsync_len = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .vsync_len = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .pixclock = 33805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .left_margin = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .right_margin = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .upper_margin = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .lower_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .hsync_len = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .vsync_len = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .yres = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .pixclock = 25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .left_margin = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .right_margin = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .upper_margin = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .lower_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .hsync_len = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .vsync_len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .xres = 854,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .pixclock = 31518,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .left_margin = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .right_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .upper_margin = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .lower_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .hsync_len = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .refresh = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .xres = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .yres = 768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .pixclock = 16886,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .left_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .right_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .upper_margin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .lower_margin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .hsync_len = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .vsync_len = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .refresh = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .xres = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .yres = 768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .pixclock = 15009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .left_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .right_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .upper_margin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .lower_margin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .hsync_len = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .vsync_len = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .xres = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .pixclock = 18939,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .left_margin = 353,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .right_margin = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .upper_margin = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .lower_margin = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .hsync_len = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .vsync_len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .xres = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .yres = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .pixclock = 13426,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .left_margin = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .right_margin = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .upper_margin = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .lower_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .hsync_len = 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .xres = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .yres = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .pixclock = 9375,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .left_margin = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .right_margin = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .upper_margin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .lower_margin = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .hsync_len = 216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .vsync_len = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .refresh = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .xres = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .yres = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .pixclock = 9380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .left_margin = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .right_margin = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .upper_margin = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .lower_margin = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .hsync_len = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .vsync_len = 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .refresh = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .xres = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .yres = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .pixclock = 9380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .left_margin = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .right_margin = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .upper_margin = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .lower_margin = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .hsync_len = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .vsync_len = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .refresh = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .xres = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .yres = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .pixclock = 5787,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .left_margin = 328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .right_margin = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .upper_margin = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .lower_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .hsync_len = 208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static char *fb_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static unsigned long default_bpp = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static enum fsl_diu_monitor_port monitor_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static char *monitor_string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #if defined(CONFIG_NOT_COHERENT_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static u8 *coherence_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static size_t coherence_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static unsigned int d_cache_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static DEFINE_SPINLOCK(diu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) enum mfb_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PLANE1_AOI0, /* Plane 1, first AOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PLANE1_AOI1, /* Plane 1, second AOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PLANE2_AOI0, /* Plane 2, first AOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PLANE2_AOI1, /* Plane 2, second AOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct mfb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) enum mfb_index index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) char *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned long pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct diu_ad *ad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned char g_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int x_aoi_d; /* aoi display x offset to physical screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int y_aoi_d; /* aoi display y offset to physical screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct fsl_diu_data *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * struct fsl_diu_data - per-DIU data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @dma_addr: DMA address of this structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @fsl_diu_info: fb_info objects, one per AOI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @dev_attr: sysfs structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @irq: IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @monitor_port: the monitor port this DIU is connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @diu_reg: pointer to the DIU hardware registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @reg_lock: spinlock for register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @dummy_aoi: video buffer for the 4x4 32-bit dummy AOI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * dummy_ad: DIU Area Descriptor for the dummy AOI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @ad[]: Area Descriptors for each real AOI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @gamma: gamma color table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @cursor: hardware cursor data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @blank_cursor: blank cursor for hiding cursor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @next_cursor: scratch space to build load cursor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * @edid_data: EDID information buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * @has_edid: whether or not the EDID buffer is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * This data structure must be allocated with 32-byte alignment, so that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * internal fields can be aligned properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct fsl_diu_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct fb_info fsl_diu_info[NUM_AOIS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct mfb_info mfb[NUM_AOIS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct device_attribute dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum fsl_diu_monitor_port monitor_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct diu __iomem *diu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 dummy_aoi[4 * 4 * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct diu_ad dummy_ad __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct diu_ad ad[NUM_AOIS] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 gamma[256 * 3] __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* It's easier to parse the cursor data as little-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __le16 cursor[MAX_CURS * MAX_CURS] __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Blank cursor data -- used to hide the cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) __le16 blank_cursor[MAX_CURS * MAX_CURS] __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Scratch cursor data -- used to build new cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __le16 next_cursor[MAX_CURS * MAX_CURS] __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) uint8_t edid_data[EDID_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) bool has_edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Determine the DMA address of a member of the fsl_diu_data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DMA_ADDR(p, f) ((p)->dma_addr + offsetof(struct fsl_diu_data, f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct mfb_info mfb_template[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .index = PLANE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .id = "Panel0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .registered = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .count = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .x_aoi_d = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .y_aoi_d = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .index = PLANE1_AOI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .id = "Panel1 AOI0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .registered = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .g_alpha = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .count = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .x_aoi_d = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .y_aoi_d = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .index = PLANE1_AOI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .id = "Panel1 AOI1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .registered = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .g_alpha = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .count = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .x_aoi_d = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .y_aoi_d = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .index = PLANE2_AOI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .id = "Panel2 AOI0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .registered = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .g_alpha = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .count = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .x_aoi_d = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .y_aoi_d = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .index = PLANE2_AOI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .id = "Panel2 AOI1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .registered = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .g_alpha = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .count = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .x_aoi_d = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .y_aoi_d = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void __attribute__ ((unused)) fsl_diu_dump(struct diu __iomem *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pr_debug("DIU: desc=%08x,%08x,%08x, gamma=%08x palette=%08x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "cursor=%08x curs_pos=%08x diu_mode=%08x bgnd=%08x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "disp_size=%08x hsyn_para=%08x vsyn_para=%08x syn_pol=%08x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "thresholds=%08x int_mask=%08x plut=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) hw->desc[0], hw->desc[1], hw->desc[2], hw->gamma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) hw->palette, hw->cursor, hw->curs_pos, hw->diu_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hw->bgnd, hw->disp_size, hw->hsyn_para, hw->vsyn_para,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) hw->syn_pol, hw->thresholds, hw->int_mask, hw->plut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * fsl_diu_name_to_port - convert a port name to a monitor port enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * the enum fsl_diu_monitor_port that corresponds to that string.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * For compatibility with older versions, a number ("0", "1", or "2") is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * If the string is unknown, DVI is assumed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * If the particular port is not supported by the platform, another port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * (platform-specific) is chosen instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!kstrtoul(s, 10, &val) && (val <= 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) port = (enum fsl_diu_monitor_port) val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) else if (strncmp(s, "lvds", 4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) port = FSL_DIU_PORT_LVDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else if (strncmp(s, "dlvds", 5) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) port = FSL_DIU_PORT_DLVDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (diu_ops.valid_monitor_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) port = diu_ops.valid_monitor_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Workaround for failed writing desc register of planes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Needed with MPC5121 DIU rev 2.0 silicon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) void wr_reg_wa(u32 *reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) out_be32(reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } while (in_be32(reg) != val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void fsl_diu_enable_panel(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct diu_ad *ad = mfbi->ad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct diu __iomem *hw = data->diu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) switch (mfbi->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case PLANE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) wr_reg_wa(&hw->desc[0], ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case PLANE1_AOI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cmfbi = &data->mfb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (cmfbi->count > 0) /* AOI1 open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ad->next_ad =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) cpu_to_le32(cmfbi->ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ad->next_ad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) wr_reg_wa(&hw->desc[1], ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case PLANE2_AOI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) cmfbi = &data->mfb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (cmfbi->count > 0) /* AOI1 open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ad->next_ad =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cpu_to_le32(cmfbi->ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ad->next_ad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) wr_reg_wa(&hw->desc[2], ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case PLANE1_AOI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pmfbi = &data->mfb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ad->next_ad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (hw->desc[1] == data->dummy_ad.paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) wr_reg_wa(&hw->desc[1], ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) else /* AOI0 open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case PLANE2_AOI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pmfbi = &data->mfb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ad->next_ad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (hw->desc[2] == data->dummy_ad.paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) wr_reg_wa(&hw->desc[2], ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) else /* AOI0 was open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void fsl_diu_disable_panel(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct diu_ad *ad = mfbi->ad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct diu __iomem *hw = data->diu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) switch (mfbi->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case PLANE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) wr_reg_wa(&hw->desc[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case PLANE1_AOI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) cmfbi = &data->mfb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (cmfbi->count > 0) /* AOI1 is open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* move AOI1 to the first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) else /* AOI1 was closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* close AOI 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case PLANE2_AOI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) cmfbi = &data->mfb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (cmfbi->count > 0) /* AOI1 is open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* move AOI1 to the first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) else /* AOI1 was closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* close AOI 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case PLANE1_AOI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pmfbi = &data->mfb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (hw->desc[1] != ad->paddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* AOI1 is not the first in the chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (pmfbi->count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* AOI0 is open, must be the first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pmfbi->ad->next_ad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else /* AOI1 is the first in the chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* close AOI 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case PLANE2_AOI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pmfbi = &data->mfb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (hw->desc[2] != ad->paddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* AOI1 is not the first in the chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (pmfbi->count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* AOI0 is open, must be the first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pmfbi->ad->next_ad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } else /* AOI1 is the first in the chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* close AOI 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void enable_lcdc(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct diu __iomem *hw = data->diu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) out_be32(&hw->diu_mode, MFB_MODE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static void disable_lcdc(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct diu __iomem *hw = data->diu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) out_be32(&hw->diu_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int available_height, upper_aoi_bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) enum mfb_index index = mfbi->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int lower_aoi_is_open, upper_aoi_is_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) __u32 base_plane_width, base_plane_height, upper_aoi_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) base_plane_width = data->fsl_diu_info[0].var.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) base_plane_height = data->fsl_diu_info[0].var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (mfbi->x_aoi_d < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mfbi->x_aoi_d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (mfbi->y_aoi_d < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mfbi->y_aoi_d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case PLANE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (mfbi->x_aoi_d != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mfbi->x_aoi_d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (mfbi->y_aoi_d != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mfbi->y_aoi_d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case PLANE1_AOI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case PLANE2_AOI0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) lower_aoi_mfbi = data->fsl_diu_info[index+1].par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (var->xres > base_plane_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) var->xres = base_plane_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) mfbi->x_aoi_d = base_plane_width - var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (lower_aoi_is_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) available_height = lower_aoi_mfbi->y_aoi_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) available_height = base_plane_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (var->yres > available_height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) var->yres = available_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if ((mfbi->y_aoi_d + var->yres) > available_height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) mfbi->y_aoi_d = available_height - var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case PLANE1_AOI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case PLANE2_AOI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) upper_aoi_mfbi = data->fsl_diu_info[index-1].par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) upper_aoi_height = data->fsl_diu_info[index-1].var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (var->xres > base_plane_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) var->xres = base_plane_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mfbi->x_aoi_d = base_plane_width - var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (mfbi->y_aoi_d < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mfbi->y_aoi_d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (upper_aoi_is_open) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (mfbi->y_aoi_d < upper_aoi_bottom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mfbi->y_aoi_d = upper_aoi_bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) available_height = base_plane_height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) - upper_aoi_bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) available_height = base_plane_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (var->yres > available_height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) var->yres = available_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mfbi->y_aoi_d = base_plane_height - var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Checks to see if the hardware supports the state requested by var passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * in. This function does not alter the hardware state! If the var passed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * is slightly off by what the hardware can support then we alter the var
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * PASSED in to what we can do. If the hardware doesn't support mode change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * a -EINVAL will be returned by the upper layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int fsl_diu_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (var->xres_virtual < var->xres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) var->xres_virtual = var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (var->yres_virtual < var->yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) var->yres_virtual = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (var->xoffset + info->var.xres > info->var.xres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) var->xoffset = info->var.xres_virtual - info->var.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (var->yoffset + info->var.yres > info->var.yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) var->yoffset = info->var.yres_virtual - info->var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (var->bits_per_pixel != 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) var->bits_per_pixel = default_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) switch (var->bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) var->red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) var->red.offset = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) var->red.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) var->green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) var->green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) var->green.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) var->blue.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) var->transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) var->transp.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) var->transp.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) var->red.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) var->red.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) var->green.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) var->blue.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) var->blue.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) var->transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) var->transp.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) var->transp.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) var->red.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) var->red.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) var->green.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) var->blue.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) var->transp.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) var->transp.offset = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) var->transp.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) var->height = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) var->width = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) var->grayscale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Copy nonstd field to/from sync for fbset usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) var->sync |= var->nonstd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) var->nonstd |= var->sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) adjust_aoi_size_position(var, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static void set_fix(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct fb_fix_screeninfo *fix = &info->fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) strncpy(fix->id, mfbi->id, sizeof(fix->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) fix->type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) fix->accel = FB_ACCEL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) fix->visual = FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) fix->xpanstep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) fix->ypanstep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static void update_lcdc(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct diu __iomem *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u8 *gamma_table_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) hw = data->diu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (diu_ops.set_monitor_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) diu_ops.set_monitor_port(data->monitor_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) gamma_table_base = data->gamma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Prep for DIU init - gamma table, cursor table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) for (i = 0; i <= 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) for (j = 0; j <= 255; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) *gamma_table_base++ = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (diu_ops.set_gamma_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) diu_ops.set_gamma_table(data->monitor_port, data->gamma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) disable_lcdc(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Program DIU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) out_be32(&hw->gamma, DMA_ADDR(data, gamma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) out_be32(&hw->bgnd, 0x007F7F7F); /* Set background to grey */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) out_be32(&hw->disp_size, (var->yres << 16) | var->xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Horizontal and vertical configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) temp = var->left_margin << 22 | /* BP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) var->hsync_len << 11 | /* PW_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) var->right_margin; /* FP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) out_be32(&hw->hsyn_para, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) temp = var->upper_margin << 22 | /* BP_V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) var->vsync_len << 11 | /* PW_V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) var->lower_margin; /* FP_V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) out_be32(&hw->vsyn_para, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) diu_ops.set_pixel_clock(var->pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #ifndef CONFIG_PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * The PLUT register is defined differently on the MPC5121 than it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * is on other SOCs. Unfortunately, there's no documentation that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * explains how it's supposed to be programmed, so for now, we leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * it at the default value on the MPC5121.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * For other SOCs, program it for the highest priority, which will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * reduce the chance of underrun. Technically, we should scale the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * priority to match the screen resolution, but doing that properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * requires delicate fine-tuning for each use-case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) out_be32(&hw->plut, 0x01F5F666);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Enable the DIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) enable_lcdc(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int map_video_memory(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 smem_len = info->fix.line_length * info->var.yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) p = alloc_pages_exact(smem_len, GFP_DMA | __GFP_ZERO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(info->dev, "unable to allocate fb memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mutex_lock(&info->mm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) info->screen_base = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) info->fix.smem_start = virt_to_phys(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) info->fix.smem_len = smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mutex_unlock(&info->mm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) info->screen_size = info->fix.smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static void unmap_video_memory(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) void *p = info->screen_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) size_t l = info->fix.smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) mutex_lock(&info->mm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) info->screen_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) info->fix.smem_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) info->fix.smem_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) mutex_unlock(&info->mm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) free_pages_exact(p, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * Using the fb_var_screeninfo in fb_info we set the aoi of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * particular framebuffer. It is a light version of fsl_diu_set_par.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int fsl_diu_set_aoi(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct diu_ad *ad = mfbi->ad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* AOI should not be greater than display size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * fsl_diu_get_pixel_format: return the pixel format for a given color depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * The pixel format is a 32-bit value that determine which bits in each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * pixel are to be used for each color. This is the default function used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * if the platform does not define its own version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define PF_BYTE_F 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define PF_ALPHA_C_MASK 0x0E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define PF_ALPHA_C_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define PF_BLUE_C_MASK 0x01800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define PF_BLUE_C_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define PF_GREEN_C_MASK 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define PF_GREEN_C_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define PF_RED_C_MASK 0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define PF_RED_C_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define PF_PALETTE 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define PF_PIXEL_S_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define PF_PIXEL_S_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define PF_COMP_3_MASK 0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define PF_COMP_3_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define PF_COMP_2_MASK 0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define PF_COMP_2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define PF_COMP_1_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define PF_COMP_1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define PF_COMP_0_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define PF_COMP_0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define MAKE_PF(alpha, red, green, blue, size, c0, c1, c2, c3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) (blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) (red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) (c2 << PF_COMP_2_SHIFT) | (c1 << PF_COMP_1_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) (c0 << PF_COMP_0_SHIFT) | (size << PF_PIXEL_S_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) switch (bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* 0x88883316 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return MAKE_PF(3, 2, 1, 0, 3, 8, 8, 8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* 0x88082219 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return MAKE_PF(4, 0, 1, 2, 2, 8, 8, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* 0x65053118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) pr_err("fsl-diu: unsupported color depth %u\n", bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Copies a cursor image from user space to the proper place in driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * memory so that the hardware can display the cursor image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * Cursor data is represented as a sequence of 'width' bits packed into bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * That is, the first 8 bits are in the first byte, the second 8 bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * second byte, and so on. Therefore, the each row of the cursor is (width +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * 7) / 8 bytes of 'data'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * The DIU only supports cursors up to 32x32 (MAX_CURS). We reject cursors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * larger than this, so we already know that 'width' <= 32. Therefore, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * simplify our code by using a 32-bit big-endian integer ("line") to read in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * a single line of pixels, and only look at the top 'width' bits of that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * integer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * This could result in an unaligned 32-bit read. For example, if the cursor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * is 24x24, then the first three bytes of 'image' contain the pixel data for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * the top line of the cursor. We do a 32-bit read of 'image', but we look
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * only at the top 24 bits. Then we increment 'image' by 3 bytes. The next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * read is unaligned. The only problem is that we might read past the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * 'image' by 1-3 bytes, but that should not cause any problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static void fsl_diu_load_cursor_image(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) const void *image, uint16_t bg, uint16_t fg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) unsigned int width, unsigned int height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) __le16 *cursor = data->cursor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) __le16 _fg = cpu_to_le16(fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) __le16 _bg = cpu_to_le16(bg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned int h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) for (h = 0; h < height; h++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) uint32_t mask = 1 << 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) uint32_t line = be32_to_cpup(image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) for (w = 0; w < width; w++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) cursor[w] = (line & mask) ? _fg : _bg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) mask >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) cursor += MAX_CURS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) image += DIV_ROUND_UP(width, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * Set a hardware cursor. The image data for the cursor is passed via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * fb_cursor object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int fsl_diu_cursor(struct fb_info *info, struct fb_cursor *cursor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct diu __iomem *hw = data->diu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* The cursor size has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (cursor->set & FB_CUR_SETSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * The DIU cursor is a fixed size, so when we get this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * message, instead of resizing the cursor, we just clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * all the image data, in expectation of new data. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * in tests this control does not appear to be normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) memset(data->cursor, 0, sizeof(data->cursor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* The cursor position has changed (cursor->image.dx|dy) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (cursor->set & FB_CUR_SETPOS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) uint32_t xx, yy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) yy = (cursor->image.dy - info->var.yoffset) & 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) xx = (cursor->image.dx - info->var.xoffset) & 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) out_be32(&hw->curs_pos, yy << 16 | xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * FB_CUR_SETIMAGE - the cursor image has changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * FB_CUR_SETCMAP - the cursor colors has changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * FB_CUR_SETSHAPE - the cursor bitmask has changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * Determine the size of the cursor image data. Normally,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * it's 8x16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) unsigned int image_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) DIV_ROUND_UP(cursor->image.width, 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) cursor->image.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) unsigned int image_words =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) DIV_ROUND_UP(image_size, sizeof(uint32_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) unsigned int bg_idx = cursor->image.bg_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) unsigned int fg_idx = cursor->image.fg_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) uint32_t *image, *source, *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) uint16_t fg, bg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (info->state != FBINFO_STATE_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ((info->cmap.green[bg_idx] & 0xf8) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) 1 << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ((info->cmap.green[fg_idx] & 0xf8) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) 1 << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* Use 32-bit operations on the data to improve performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) image = (uint32_t *)data->next_cursor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) source = (uint32_t *)cursor->image.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) mask = (uint32_t *)cursor->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (cursor->rop == ROP_XOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) for (i = 0; i < image_words; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) image[i] = source[i] ^ mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) for (i = 0; i < image_words; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) image[i] = source[i] & mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) fsl_diu_load_cursor_image(info, image, bg, fg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) cursor->image.width, cursor->image.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * Show or hide the cursor. The cursor data is always stored in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * 'cursor' memory block, and the actual cursor position is always in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * the DIU's CURS_POS register. To hide the cursor, we redirect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * CURSOR register to a blank cursor. The show the cursor, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * redirect the CURSOR register to the real cursor data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (cursor->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) out_be32(&hw->cursor, DMA_ADDR(data, cursor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) out_be32(&hw->cursor, DMA_ADDR(data, blank_cursor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * Using the fb_var_screeninfo in fb_info we set the resolution of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * particular framebuffer. This function alters the fb_fix_screeninfo stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * in fb_info. It does not alter var in fb_info since we are using that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * data. This means we depend on the data in var inside fb_info to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * supported by the hardware. fsl_diu_check_var is always called before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * fsl_diu_set_par to ensure this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static int fsl_diu_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) unsigned long len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct diu_ad *ad = mfbi->ad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct diu __iomem *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) hw = data->diu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) set_fix(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) len = info->var.yres_virtual * info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Alloc & dealloc each time resolution/bpp change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (len != info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (info->fix.smem_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) unmap_video_memory(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* Memory allocation for framebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (map_video_memory(info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev_err(info->dev, "unable to allocate fb memory 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (diu_ops.get_pixel_format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ad->pix_fmt = diu_ops.get_pixel_format(data->monitor_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ad->pix_fmt = fsl_diu_get_pixel_format(var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ad->addr = cpu_to_le32(info->fix.smem_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) var->xres_virtual) | mfbi->g_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* AOI should not be greater than display size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* Disable chroma keying function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ad->ckmax_r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ad->ckmax_g = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ad->ckmax_b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ad->ckmin_r = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ad->ckmin_g = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ad->ckmin_b = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (mfbi->index == PLANE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) update_lcdc(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return ((val << width) + 0x7FFF - val) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * Set a single color register. The values supplied have a 16 bit magnitude
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * which needs to be scaled in this function for the hardware. Things to take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * into consideration are how many color registers, if any, are supported with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * the current color visual. With truecolor mode no color palettes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * supported. Here a pseudo palette is created which we store the value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * color palette.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) unsigned int green, unsigned int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) unsigned int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * If greyscale is true, then we convert the RGB value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * to greyscale no matter what visual we are using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (info->var.grayscale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) red = green = blue = (19595 * red + 38470 * green +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) 7471 * blue) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) switch (info->fix.visual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) case FB_VISUAL_TRUECOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * 16-bit True Colour. We encode the RGB value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * according to the RGB bitfield information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (regno < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u32 *pal = info->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) red = CNVT_TOHW(red, info->var.red.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) green = CNVT_TOHW(green, info->var.green.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) blue = CNVT_TOHW(blue, info->var.blue.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) transp = CNVT_TOHW(transp, info->var.transp.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) v = (red << info->var.red.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) (green << info->var.green.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) (blue << info->var.blue.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) (transp << info->var.transp.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pal[regno] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * Pan (or wrap, depending on the `vmode' field) the display using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * don't fit, return -EINVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if ((info->var.xoffset == var->xoffset) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) (info->var.yoffset == var->yoffset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return 0; /* No change, do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (var->xoffset + info->var.xres > info->var.xres_virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) || var->yoffset + info->var.yres > info->var.yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) info->var.xoffset = var->xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) info->var.yoffset = var->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (var->vmode & FB_VMODE_YWRAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) info->var.vmode |= FB_VMODE_YWRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) info->var.vmode &= ~FB_VMODE_YWRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) fsl_diu_set_aoi(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct diu_ad *ad = mfbi->ad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct mfb_chroma_key ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) unsigned char global_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct aoi_display_offset aoi_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) __u32 pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) void __user *buf = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) dev_dbg(info->dev, "ioctl %08x (dir=%s%s type=%u nr=%u size=%u)\n", cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) _IOC_DIR(cmd) & _IOC_READ ? "R" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) _IOC_DIR(cmd) & _IOC_WRITE ? "W" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) _IOC_TYPE(cmd), _IOC_NR(cmd), _IOC_SIZE(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case MFB_SET_PIXFMT_OLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dev_warn(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) "MFB_SET_PIXFMT value of 0x%08x is deprecated.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) MFB_SET_PIXFMT_OLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) case MFB_SET_PIXFMT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ad->pix_fmt = pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) case MFB_GET_PIXFMT_OLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev_warn(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) "MFB_GET_PIXFMT value of 0x%08x is deprecated.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) MFB_GET_PIXFMT_OLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case MFB_GET_PIXFMT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) pix_fmt = ad->pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case MFB_SET_AOID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) mfbi->x_aoi_d = aoi_d.x_aoi_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) mfbi->y_aoi_d = aoi_d.y_aoi_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) fsl_diu_check_var(&info->var, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) fsl_diu_set_aoi(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) case MFB_GET_AOID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) aoi_d.x_aoi_d = mfbi->x_aoi_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) aoi_d.y_aoi_d = mfbi->y_aoi_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) case MFB_GET_ALPHA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) global_alpha = mfbi->g_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) case MFB_SET_ALPHA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* set panel information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) (global_alpha & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) mfbi->g_alpha = global_alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) case MFB_SET_CHROMA_KEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* set panel winformation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (copy_from_user(&ck, buf, sizeof(ck)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (ck.enable &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) (ck.red_max < ck.red_min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ck.green_max < ck.green_min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ck.blue_max < ck.blue_min))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (!ck.enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ad->ckmax_r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ad->ckmax_g = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ad->ckmax_b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ad->ckmin_r = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ad->ckmin_g = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ad->ckmin_b = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ad->ckmax_r = ck.red_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ad->ckmax_g = ck.green_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ad->ckmax_b = ck.blue_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ad->ckmin_r = ck.red_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) ad->ckmin_g = ck.green_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ad->ckmin_b = ck.blue_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #ifdef CONFIG_PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) case MFB_SET_GAMMA: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (copy_from_user(data->gamma, buf, sizeof(data->gamma)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) setbits32(&data->diu_reg->gamma, 0); /* Force table reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) case MFB_GET_GAMMA: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (copy_to_user(buf, data->gamma, sizeof(data->gamma)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static inline void fsl_diu_enable_interrupts(struct fsl_diu_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) u32 int_mask = INT_UNDRUN; /* enable underrun detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (IS_ENABLED(CONFIG_NOT_COHERENT_CACHE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) int_mask |= INT_VSYNC; /* enable vertical sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) clrbits32(&data->diu_reg->int_mask, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* turn on fb if count == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static int fsl_diu_open(struct fb_info *info, int user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* free boot splash memory on first /dev/fb0 open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if ((mfbi->index == PLANE0) && diu_ops.release_bootmem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) diu_ops.release_bootmem();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) spin_lock(&diu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mfbi->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (mfbi->count == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) fsl_diu_check_var(&info->var, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) res = fsl_diu_set_par(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) mfbi->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) fsl_diu_enable_interrupts(mfbi->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) fsl_diu_enable_panel(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) spin_unlock(&diu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* turn off fb if count == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static int fsl_diu_release(struct fb_info *info, int user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) spin_lock(&diu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) mfbi->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (mfbi->count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) bool disable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* Disable interrupts only if all AOIs are closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) for (i = 0; i < NUM_AOIS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct mfb_info *mi = data->fsl_diu_info[i].par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (mi->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) disable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) out_be32(&data->diu_reg->int_mask, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) fsl_diu_disable_panel(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) spin_unlock(&diu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static const struct fb_ops fsl_diu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .fb_check_var = fsl_diu_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .fb_set_par = fsl_diu_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .fb_setcolreg = fsl_diu_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .fb_pan_display = fsl_diu_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .fb_ioctl = fsl_diu_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .fb_open = fsl_diu_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .fb_release = fsl_diu_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .fb_cursor = fsl_diu_cursor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static int install_fb(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct fsl_diu_data *data = mfbi->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) const char *aoi_mode, *init_aoi_mode = "320x240";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct fb_videomode *db = fsl_diu_mode_db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) int has_default_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) info->var.activate = FB_ACTIVATE_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) info->fbops = &fsl_diu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) info->flags = FBINFO_DEFAULT | FBINFO_VIRTFB | FBINFO_PARTIAL_PAN_OK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) FBINFO_READS_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) info->pseudo_palette = mfbi->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) rc = fb_alloc_cmap(&info->cmap, 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (mfbi->index == PLANE0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (data->has_edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* Now build modedb from EDID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) fb_edid_to_monspecs(data->edid_data, &info->monspecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) fb_videomode_to_modelist(info->monspecs.modedb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) info->monspecs.modedb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) db = info->monspecs.modedb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dbsize = info->monspecs.modedb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) aoi_mode = fb_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) aoi_mode = init_aoi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) default_bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * For plane 0 we continue and look into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * driver's internal modedb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if ((mfbi->index == PLANE0) && data->has_edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) has_default_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!has_default_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) has_default_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* Still not found, use preferred mode from database if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (!has_default_mode && info->monspecs.modedb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct fb_monspecs *specs = &info->monspecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct fb_videomode *modedb = &specs->modedb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * Get preferred timing. If not found,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * first mode in database will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (specs->misc & FB_MISC_1ST_DETAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) for (i = 0; i < specs->modedb_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) modedb = &specs->modedb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) info->var.bits_per_pixel = default_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) fb_videomode_to_var(&info->var, modedb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (fsl_diu_check_var(&info->var, info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dev_err(info->dev, "fsl_diu_check_var failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) unmap_video_memory(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (register_framebuffer(info) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) dev_err(info->dev, "register_framebuffer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) unmap_video_memory(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) mfbi->registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_info(info->dev, "%s registered successfully\n", mfbi->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static void uninstall_fb(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct mfb_info *mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (!mfbi->registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) unmap_video_memory(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) mfbi->registered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) struct diu __iomem *hw = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) uint32_t status = in_be32(&hw->int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* This is the workaround for underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (status & INT_UNDRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) out_be32(&hw->diu_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) out_be32(&hw->diu_mode, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #if defined(CONFIG_NOT_COHERENT_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) else if (status & INT_VSYNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) for (i = 0; i < coherence_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) i += d_cache_line_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) __asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) "dcbz 0, %[input]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ::[input]"r"(&coherence_data[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) * Power management hooks. Note that we won't be called from IRQ context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) * unlike the blank functions above, so we may sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct fsl_diu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) data = dev_get_drvdata(&ofdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) disable_lcdc(data->fsl_diu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static int fsl_diu_resume(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct fsl_diu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) data = dev_get_drvdata(&ofdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) fsl_diu_enable_interrupts(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) update_lcdc(data->fsl_diu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) for (i = 0; i < NUM_AOIS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (data->mfb[i].count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) fsl_diu_enable_panel(&data->fsl_diu_info[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define fsl_diu_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define fsl_diu_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static ssize_t store_monitor(struct device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) enum fsl_diu_monitor_port old_monitor_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct fsl_diu_data *data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) container_of(attr, struct fsl_diu_data, dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) old_monitor_port = data->monitor_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) data->monitor_port = fsl_diu_name_to_port(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (old_monitor_port != data->monitor_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* All AOIs need adjust pixel format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * fsl_diu_set_par only change the pixsel format here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * unlikely to fail. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) for (i=0; i < NUM_AOIS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) fsl_diu_set_par(&data->fsl_diu_info[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static ssize_t show_monitor(struct device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct fsl_diu_data *data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) container_of(attr, struct fsl_diu_data, dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) switch (data->monitor_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) case FSL_DIU_PORT_DVI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return sprintf(buf, "DVI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) case FSL_DIU_PORT_LVDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return sprintf(buf, "Single-link LVDS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) case FSL_DIU_PORT_DLVDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return sprintf(buf, "Dual-link LVDS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static int fsl_diu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) struct mfb_info *mfbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct fsl_diu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) dma_addr_t dma_addr; /* DMA addr of fsl_diu_data struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) const void *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) data = dmam_alloc_coherent(&pdev->dev, sizeof(struct fsl_diu_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) &dma_addr, GFP_DMA | __GFP_ZERO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) data->dma_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * dma_alloc_coherent() uses a page allocator, so the address is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) * always page-aligned. We need the memory to be 32-byte aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * so that's good. However, if one day the allocator changes, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * need to catch that. It's not worth the effort to handle unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * alloctions now because it's highly unlikely to ever be a problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if ((unsigned long)data & 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) dev_err(&pdev->dev, "misaligned allocation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) spin_lock_init(&data->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) for (i = 0; i < NUM_AOIS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) struct fb_info *info = &data->fsl_diu_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) info->device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) info->par = &data->mfb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) * We store the physical address of the AD in the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) * 'paddr' field of the AD itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) data->ad[i].paddr = DMA_ADDR(data, ad[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) info->fix.smem_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* Initialize the AOI data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) mfbi = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) mfbi->parent = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) mfbi->ad = &data->ad[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /* Get the EDID data from the device tree, if present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) prop = of_get_property(np, "edid", &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (prop && ret == EDID_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) memcpy(data->edid_data, prop, EDID_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) data->has_edid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) data->diu_reg = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (!data->diu_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) dev_err(&pdev->dev, "cannot map DIU registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /* Get the IRQ of the DIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) data->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (!data->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) dev_err(&pdev->dev, "could not get DIU IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) data->monitor_port = monitor_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* Initialize the dummy Area Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) data->dummy_ad.addr = cpu_to_le32(DMA_ADDR(data, dummy_aoi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) data->dummy_ad.pix_fmt = 0x88882317;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) data->dummy_ad.src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) data->dummy_ad.aoi_size = cpu_to_le32((4 << 16) | 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) data->dummy_ad.offset_xyi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) data->dummy_ad.offset_xyd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) data->dummy_ad.next_ad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) data->dummy_ad.paddr = DMA_ADDR(data, dummy_ad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * Let DIU continue to display splash screen if it was pre-initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * by the bootloader; otherwise, clear the display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (in_be32(&data->diu_reg->diu_mode) == MFB_MODE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) out_be32(&data->diu_reg->desc[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) * Older versions of U-Boot leave interrupts enabled, so disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * all of them and clear the status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) out_be32(&data->diu_reg->int_mask, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) in_be32(&data->diu_reg->int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) data->diu_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) dev_err(&pdev->dev, "could not claim irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) for (i = 0; i < NUM_AOIS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ret = install_fb(&data->fsl_diu_info[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) dev_err(&pdev->dev, "could not register fb %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) free_irq(data->irq, data->diu_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) sysfs_attr_init(&data->dev_attr.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) data->dev_attr.attr.name = "monitor";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) data->dev_attr.show = show_monitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) data->dev_attr.store = store_monitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ret = device_create_file(&pdev->dev, &data->dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) dev_err(&pdev->dev, "could not create sysfs file %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) data->dev_attr.attr.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) dev_set_drvdata(&pdev->dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) for (i = 0; i < NUM_AOIS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) uninstall_fb(&data->fsl_diu_info[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) iounmap(data->diu_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static int fsl_diu_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct fsl_diu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) data = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) disable_lcdc(&data->fsl_diu_info[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) free_irq(data->irq, data->diu_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) for (i = 0; i < NUM_AOIS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) uninstall_fb(&data->fsl_diu_info[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) iounmap(data->diu_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static int __init fsl_diu_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) char *opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) while ((opt = strsep(&options, ",")) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (!*opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (!strncmp(opt, "monitor=", 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) monitor_port = fsl_diu_name_to_port(opt + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) } else if (!strncmp(opt, "bpp=", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (!kstrtoul(opt + 4, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) default_bpp = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) fb_mode = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static const struct of_device_id fsl_diu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #ifdef CONFIG_PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .compatible = "fsl,mpc5121-diu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .compatible = "fsl,diu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) MODULE_DEVICE_TABLE(of, fsl_diu_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static struct platform_driver fsl_diu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .name = "fsl-diu-fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .of_match_table = fsl_diu_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .probe = fsl_diu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .remove = fsl_diu_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .suspend = fsl_diu_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .resume = fsl_diu_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static int __init fsl_diu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #ifdef CONFIG_NOT_COHERENT_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) const u32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) char *option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * For kernel boot options (in 'video=xxxfb:<options>' format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (fb_get_options("fslfb", &option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) fsl_diu_setup(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) monitor_port = fsl_diu_name_to_port(monitor_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * Must to verify set_pixel_clock. If not implement on platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * then that means that there is no platform support for the DIU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (!diu_ops.set_pixel_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #ifdef CONFIG_NOT_COHERENT_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) np = of_get_cpu_node(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) prop = of_get_property(np, "d-cache-size", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (prop == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) pr_err("fsl-diu-fb: missing 'd-cache-size' property' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) "in 'cpu' node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) * Freescale PLRU requires 13/8 times the cache size to do a proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) * displacement flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) coherence_data_size = be32_to_cpup(prop) * 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) coherence_data_size /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) pr_debug("fsl-diu-fb: coherence data size is %zu bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) coherence_data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) prop = of_get_property(np, "d-cache-line-size", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (prop == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) "in 'cpu' node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) d_cache_line_size = be32_to_cpup(prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) pr_debug("fsl-diu-fb: cache lines size is %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) d_cache_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) coherence_data = vmalloc(coherence_data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (!coherence_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ret = platform_driver_register(&fsl_diu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) pr_err("fsl-diu-fb: failed to register platform driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #if defined(CONFIG_NOT_COHERENT_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) vfree(coherence_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static void __exit fsl_diu_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) platform_driver_unregister(&fsl_diu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #if defined(CONFIG_NOT_COHERENT_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) vfree(coherence_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) module_init(fsl_diu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) module_exit(fsl_diu_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) module_param_named(mode, fb_mode, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) MODULE_PARM_DESC(mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) module_param_named(bpp, default_bpp, ulong, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) module_param_named(monitor, monitor_string, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) MODULE_PARM_DESC(monitor, "Specify the monitor port "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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