^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/video/edid.h - EDID/DDC Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 1. XFree86 4.3.0, edid.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 2. John Fremlin <vii@users.sourceforge.net> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ani Joshi <ajoshi@unixbox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * DDC is a Trademark of VESA (Video Electronics Standard Association).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __EDID_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __EDID_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EDID_LENGTH 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EDID_HEADER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EDID_HEADER_END 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ID_MANUFACTURER_NAME 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ID_MANUFACTURER_NAME_END 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ID_MODEL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ID_SERIAL_NUMBER 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MANUFACTURE_WEEK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MANUFACTURE_YEAR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EDID_STRUCT_VERSION 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EDID_STRUCT_REVISION 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EDID_STRUCT_DISPLAY 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DPMS_FLAGS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ESTABLISHED_TIMING_1 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ESTABLISHED_TIMING_2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MANUFACTURERS_TIMINGS 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* standard timings supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STD_TIMING 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STD_TIMING_DESCRIPTION_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STD_TIMING_DESCRIPTIONS_START 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DETAILED_TIMING_DESCRIPTIONS_START 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DETAILED_TIMING_DESCRIPTION_SIZE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NO_DETAILED_TIMING_DESCRIPTIONS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DETAILED_TIMING_DESCRIPTION_1 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DETAILED_TIMING_DESCRIPTION_2 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DETAILED_TIMING_DESCRIPTION_3 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DETAILED_TIMING_DESCRIPTION_4 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DESCRIPTOR_DATA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UPPER_NIBBLE( x ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (((128|64|32|16) & (x)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LOWER_NIBBLE( x ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ((1|2|4|8) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define COMBINE_HI_8LO( hi, lo ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ( (((unsigned)hi) << 8) | (unsigned)lo )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define COMBINE_HI_4LO( hi, lo ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ( (((unsigned)hi) << 4) | (unsigned)lo )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PIXEL_CLOCK_LO (unsigned)block[ 0 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PIXEL_CLOCK_HI (unsigned)block[ 1 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PIXEL_CLOCK (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define H_ACTIVE_LO (unsigned)block[ 2 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define H_BLANKING_LO (unsigned)block[ 3 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define H_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 4 ] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define H_ACTIVE COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define H_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 4 ] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define H_BLANKING COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define V_ACTIVE_LO (unsigned)block[ 5 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define V_BLANKING_LO (unsigned)block[ 6 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define V_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 7 ] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define V_ACTIVE COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define V_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 7 ] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define V_BLANKING COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define H_SYNC_OFFSET_LO (unsigned)block[ 8 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define H_SYNC_WIDTH_LO (unsigned)block[ 9 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define V_SYNC_OFFSET_LO UPPER_NIBBLE( (unsigned)block[ 10 ] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define V_SYNC_WIDTH_LO LOWER_NIBBLE( (unsigned)block[ 10 ] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define V_SYNC_WIDTH_HI ((unsigned)block[ 11 ] & (1|2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define V_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (4|8)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define H_SYNC_WIDTH_HI (((unsigned)block[ 11 ] & (16|32)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define H_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (64|128)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define V_SYNC_WIDTH COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define V_SYNC_OFFSET COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define H_SYNC_WIDTH COMBINE_HI_8LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define H_SYNC_OFFSET COMBINE_HI_8LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define H_SIZE_LO (unsigned)block[ 12 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define V_SIZE_LO (unsigned)block[ 13 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define H_SIZE_HI UPPER_NIBBLE( (unsigned)block[ 14 ] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define V_SIZE_HI LOWER_NIBBLE( (unsigned)block[ 14 ] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define H_SIZE COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define V_SIZE COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define H_BORDER (unsigned)block[ 15 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define V_BORDER (unsigned)block[ 16 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FLAGS (unsigned)block[ 17 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INTERLACED (FLAGS&128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SYNC_TYPE (FLAGS&3<<3) /* bits 4,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SYNC_SEPARATE (3<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HSYNC_POSITIVE (FLAGS & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VSYNC_POSITIVE (FLAGS & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define V_MIN_RATE block[ 5 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define V_MAX_RATE block[ 6 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define H_MIN_RATE block[ 7 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define H_MAX_RATE block[ 8 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MAX_PIXEL_CLOCK (((int)block[ 9 ]) * 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GTF_SUPPORT block[10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DPMS_ACTIVE_OFF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DPMS_SUSPEND (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DPMS_STANDBY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif /* __EDID_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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