^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/amigahw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/amigaints.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/apollohw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* apollo video HW definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Control Registers. IOBASE + $x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Note: these are the Memory/IO BASE definitions for a mono card set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * alternate address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Control 3A and 3B serve identical functions except that 3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * deals with control 1 and 3b deals with Color LUT reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AP_IOBASE 0x3b0 /* Base address of 1 plane board. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AP_STATUS isaIO2mem(AP_IOBASE+0) /* Status register. Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AP_WRITE_ENABLE isaIO2mem(AP_IOBASE+0) /* Write Enable Register Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AP_DEVICE_ID isaIO2mem(AP_IOBASE+1) /* Device ID Register. Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AP_ROP_1 isaIO2mem(AP_IOBASE+2) /* Raster Operation reg. Write Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AP_DIAG_MEM_REQ isaIO2mem(AP_IOBASE+4) /* Diagnostic Memory Request. Write Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AP_CONTROL_0 isaIO2mem(AP_IOBASE+8) /* Control Register 0. Read/Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AP_CONTROL_1 isaIO2mem(AP_IOBASE+0xa) /* Control Register 1. Read/Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AP_CONTROL_3A isaIO2mem(AP_IOBASE+0xe) /* Control Register 3a. Read/Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AP_CONTROL_2 isaIO2mem(AP_IOBASE+0xc) /* Control Register 2. Read/Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FRAME_BUFFER_START 0x0FA0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FRAME_BUFFER_LEN 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* CREG 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VECTOR_MODE 0x40 /* 010x.xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DBLT_MODE 0x80 /* 100x.xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NORMAL_MODE 0xE0 /* 111x.xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SHIFT_BITS 0x1F /* xxx1.1111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* other bits are Shift value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* CREG 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD_BLT 0x80 /* 1xxx.xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NORMAL 0x80 /* 1xxx.xxxx */ /* What is happening here ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define INVERSE 0x00 /* 0xxx.xxxx */ /* Clearing this reverses the screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PIX_BLT 0x00 /* 0xxx.xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AD_HIBIT 0x40 /* xIxx.xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ROP_EN 0x10 /* xxx1.xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DST_EQ_SRC 0x00 /* xxx0.xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define nRESET_SYNC 0x08 /* xxxx.1xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SYNC_ENAB 0x02 /* xxxx.xx1x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BLANK_DISP 0x00 /* xxxx.xxx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ENAB_DISP 0x01 /* xxxx.xxx1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NORM_CREG1 (nRESET_SYNC | SYNC_ENAB | ENAB_DISP) /* no reset sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* CREG 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Following 3 defines are common to 1, 4 and 8 plane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S_DATA_1s 0x00 /* 00xx.xxxx */ /* set source to all 1's -- vector drawing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S_DATA_PIX 0x40 /* 01xx.xxxx */ /* takes source from ls-bits and replicates over 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S_DATA_PLN 0xC0 /* 11xx.xxxx */ /* normal, each data access =16-bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) one plane of image mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* CREG 3A/CREG 3B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define RESET_CREG 0x80 /* 1000.0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* ROP REG - all one nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* ********* NOTE : this is used r0,r1,r2,r3 *********** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ROP(r2,r3,r0,r1) ( (U_SHORT)((r0)|((r1)<<4)|((r2)<<8)|((r3)<<12)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DEST_ZERO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SRC_AND_DEST 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SRC_AND_nDEST 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SRC 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define nSRC_AND_DEST 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DEST 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SRC_XOR_DEST 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SRC_OR_DEST 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SRC_NOR_DEST 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SRC_XNOR_DEST 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define nDEST 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SRC_OR_nDEST 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define nSRC 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define nSRC_OR_DEST 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SRC_NAND_DEST 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DEST_ONE 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SWAP(A) ((A>>8) | ((A&0xff) <<8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* frame buffer operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int dnfb_blank(int blank, struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct fb_ops dn_fb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .fb_blank = dnfb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .fb_copyarea = dnfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct fb_var_screeninfo dnfb_var = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .xres = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .yres = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .xres_virtual = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .yres_virtual = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .bits_per_pixel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .height = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .width = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .vmode = FB_VMODE_NONINTERLACED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct fb_fix_screeninfo dnfb_fix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .id = "Apollo Mono",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .smem_start = (FRAME_BUFFER_START + IO_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .smem_len = FRAME_BUFFER_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .visual = FB_VISUAL_MONO10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .line_length = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int dnfb_blank(int blank, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (blank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) out_8(AP_CONTROL_3A, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) out_8(AP_CONTROL_3A, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int incr, y_delta, pre_read = 0, x_end, x_word_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uint start_mask, end_mask, dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ushort *src, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) short i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) incr = (area->dy <= area->sy) ? 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) src = (ushort *)(info->screen_base + area->sy * info->fix.line_length +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) (area->sx >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dest = area->dy * (info->fix.line_length >> 1) + (area->dx >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (incr > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) y_delta = (info->fix.line_length * 8) - area->sx - area->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) x_end = area->dx + area->width - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) x_word_count = (x_end >> 4) - (area->dx >> 4) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) start_mask = 0xffff0000 >> (area->dx & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) end_mask = 0x7ffff >> (x_end & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) out_8(AP_CONTROL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (((area->dx & 0xf) - (area->sx & 0xf)) % 16) | (0x4 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if ((area->dx & 0xf) < (area->sx & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pre_read = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) y_delta = -((info->fix.line_length * 8) - area->sx - area->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) x_end = area->dx - area->width + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) x_word_count = (area->dx >> 4) - (x_end >> 4) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) start_mask = 0x7ffff >> (area->dx & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) end_mask = 0xffff0000 >> (x_end & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out_8(AP_CONTROL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ((-((area->sx & 0xf) - (area->dx & 0xf))) % 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (0x4 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if ((area->dx & 0xf) > (area->sx & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pre_read = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) for (i = 0; i < area->height; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) out_8(AP_CONTROL_3A, 0xc | (dest >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (pre_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dummy = *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) src += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (x_word_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) out_8(AP_WRITE_ENABLE, start_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *src = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) src += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dest += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) out_8(AP_WRITE_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (j = 1; j < (x_word_count - 1); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *src = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) src += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dest += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) out_8(AP_WRITE_ENABLE, start_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *src = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dest += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) src += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) out_8(AP_WRITE_ENABLE, start_mask | end_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *src = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dest += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) src += incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) src += (y_delta / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dest += (y_delta / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) out_8(AP_CONTROL_0, NORMAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int dnfb_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) info = framebuffer_alloc(0, &dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) info->fbops = &dn_fb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) info->fix = dnfb_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) info->var = dnfb_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) info->var.red.length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) info->var.red.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) info->var.green = info->var.blue = info->var.red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) info->screen_base = (u_char *) info->fix.smem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) err = fb_alloc_cmap(&info->cmap, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto release_framebuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) err = register_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) goto release_framebuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) platform_set_drvdata(dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* now we have registered we can safely setup the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) out_8(AP_CONTROL_3A, RESET_CREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) out_be16(AP_WRITE_ENABLE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) out_8(AP_CONTROL_0, NORMAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) out_8(AP_CONTROL_1, (AD_BLT | DST_EQ_SRC | NORM_CREG1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) out_8(AP_CONTROL_2, S_DATA_PLN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) out_be16(AP_ROP_1, SWAP(0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) printk("apollo frame buffer alive and kicking !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) release_framebuffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct platform_driver dnfb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .probe = dnfb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "dnfb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct platform_device dnfb_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .name = "dnfb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int __init dnfb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!MACH_IS_APOLLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (fb_get_options("dnfb", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = platform_driver_register(&dnfb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = platform_device_register(&dnfb_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) platform_driver_unregister(&dnfb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) module_init(dnfb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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