^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/video/cyber2000fb.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998-2000 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Integraphics Cyber2000 frame buffer device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Internal CyberPro sizes and offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MMIO_OFFSET 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MMIO_SIZE 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NR_PALETTE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #if defined(DEBUG) && defined(CONFIG_DEBUG_LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static void debug_printf(char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern void printascii(const char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) char buffer[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) va_list ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) va_start(ap, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) vsprintf(buffer, fmt, ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) va_end(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) printascii(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define debug_printf(x...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RAMDAC_RAMPWRDN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RAMDAC_DAC8BIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RAMDAC_VREFEN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RAMDAC_BYPASS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RAMDAC_DACPWRDN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EXT_CRT_VRTOFL 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EXT_CRT_VRTOFL_LINECOMP10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXT_CRT_VRTOFL_INTERLACE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EXT_CRT_IRQ 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EXT_CRT_IRQ_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EXT_CRT_IRQ_ACT_HIGH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EXT_CRT_TEST 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EXT_SYNC_CTL 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EXT_SYNC_CTL_HS_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EXT_SYNC_CTL_HS_0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EXT_SYNC_CTL_HS_1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EXT_SYNC_CTL_HS_HSVS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EXT_SYNC_CTL_VS_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EXT_SYNC_CTL_VS_0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EXT_SYNC_CTL_VS_1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EXT_SYNC_CTL_VS_COMP 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EXT_BUS_CTL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EXT_BUS_CTL_LIN_1MB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXT_BUS_CTL_LIN_2MB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EXT_BUS_CTL_LIN_4MB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EXT_BUS_CTL_ZEROWAIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EXT_BUS_CTL_PCIBURST_WRITE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EXT_BUS_CTL_PCIBURST_READ 0x80 /* CyberPro 5000 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EXT_SEG_WRITE_PTR 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EXT_SEG_READ_PTR 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EXT_BIU_MISC 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EXT_BIU_MISC_LIN_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EXT_BIU_MISC_COP_ENABLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EXT_BIU_MISC_COP_BFC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EXT_FUNC_CTL 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EXT_FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCI_BM_CTL 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCI_BM_CTL_BURST 0x02 /* enable burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCI_BM_CTL_BACK2BACK 0x04 /* enable back to back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCI_BM_CTL_DUMMY 0x08 /* insert dummy cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define X_V2_VID_MEM_START 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define X_V2_VID_SRC_WIDTH 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define X_V2_X_START 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define X_V2_X_END 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define X_V2_Y_START 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define X_V2_Y_END 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define X_V2_VID_SRC_WIN_WIDTH 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define Y_V2_DDA_X_INC 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define Y_V2_DDA_Y_INC 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define Y_V2_VID_FIFO_CTL 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define Y_V2_VID_FMT 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define Y_V2_VID_DISP_CTL1 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define Y_V2_VID_FIFO_CTL1 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define J_X2_VID_MEM_START 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define J_X2_VID_SRC_WIDTH 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define J_X2_X_START 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define J_X2_X_END 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define J_X2_Y_START 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define J_X2_Y_END 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define J_X2_VID_SRC_WIN_WIDTH 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define K_X2_DDA_X_INIT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define K_X2_DDA_X_INC 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define K_X2_DDA_Y_INIT 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define K_X2_DDA_Y_INC 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define K_X2_VID_FMT 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define K_X2_VID_DISP_CTL1 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define K_CAP_X2_CTL1 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CURS_H_START 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CURS_H_PRESET 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CURS_V_START 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CURS_V_PRESET 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CURS_CTL 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EXT_ATTRIB_CTL 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EXT_ATTRIB_CTL_EXT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EXT_OVERSCAN_RED 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EXT_OVERSCAN_GREEN 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EXT_OVERSCAN_BLUE 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CAP_X_START 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CAP_X_END 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CAP_Y_START 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CAP_Y_END 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CAP_DDA_X_INIT 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CAP_DDA_X_INC 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CAP_DDA_Y_INIT 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CAP_DDA_Y_INC 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EXT_MEM_CTL0 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EXT_MEM_CTL0_7CLK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EXT_MEM_CTL0_RAS_1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EXT_MEM_CTL0_RAS2CAS_1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EXT_MEM_CTL0_MULTCAS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EXT_MEM_CTL0_ASYM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EXT_MEM_CTL0_CAS1ON 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EXT_MEM_CTL0_FIFOFLUSH 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EXT_MEM_CTL0_SEQRESET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EXT_MEM_CTL1 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define EXT_MEM_CTL1_PAR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EXT_MEM_CTL1_SERPAR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EXT_MEM_CTL1_SER 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EXT_MEM_CTL1_SYNC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EXT_MEM_CTL1_VRAM 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EXT_MEM_CTL1_4K_REFRESH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EXT_MEM_CTL1_256Kx4 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EXT_MEM_CTL1_512Kx8 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EXT_MEM_CTL1_1Mx16 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EXT_MEM_CTL2 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MEM_CTL2_SIZE_1MB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MEM_CTL2_SIZE_2MB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MEM_CTL2_SIZE_4MB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MEM_CTL2_SIZE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MEM_CTL2_64BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EXT_HIDDEN_CTL1 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EXT_FIFO_CTL 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EXT_SEQ_MISC 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define EXT_SEQ_MISC_8 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EXT_SEQ_MISC_16_RGB565 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define EXT_SEQ_MISC_32 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EXT_SEQ_MISC_24_RGB888 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EXT_SEQ_MISC_16_RGB555 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EXT_SEQ_MISC_8_RGB332 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EXT_SEQ_MISC_16_RGB444 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EXT_HIDDEN_CTL4 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CURS_MEM_START 0x7e /* bits 23..12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CAP_PIP_X_START 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CAP_PIP_X_END 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CAP_PIP_Y_START 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CAP_PIP_Y_END 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EXT_CAP_CTL1 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EXT_CAP_CTL2 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EXT_CAP_CTL2_ODDFRAMEIRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EXT_CAP_CTL2_ANYFRAMEIRQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BM_CTRL0 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define BM_CTRL1 0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EXT_CAP_MODE1 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EXT_CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define EXT_CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EXT_CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EXT_CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EXT_CAP_MODE1_MIRRORY 0x40 /* mirror vertically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EXT_CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define EXT_CAP_MODE2 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EXT_CAP_MODE2_CCIRINVOE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define EXT_CAP_MODE2_CCIRINVVGT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EXT_CAP_MODE2_CCIRINVHGT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EXT_CAP_MODE2_CCIRINVDG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EXT_CAP_MODE2_DATEND 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EXT_CAP_MODE2_CCIRDGH 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define EXT_CAP_MODE2_FIXSONY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define EXT_CAP_MODE2_SYNCFREEZE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define EXT_TV_CTL 0xae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define EXT_DCLK_MULT 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define EXT_DCLK_DIV 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EXT_DCLK_DIV_VFSEL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EXT_MCLK_MULT 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define EXT_MCLK_DIV 0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define EXT_LATCH1 0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define EXT_LATCH1_VAFC_EN 0x01 /* enable VAFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define EXT_FEATURE 0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define EXT_FEATURE_BUS_MASK 0x07 /* host bus mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define EXT_FEATURE_BUS_PCI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define EXT_FEATURE_BUS_VL_STD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define EXT_FEATURE_BUS_VL_LINEAR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define EXT_FEATURE_1682 0x20 /* IGS 1682 compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define EXT_LATCH2 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define EXT_LATCH2_I2C_CLKEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define EXT_LATCH2_I2C_CLK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define EXT_LATCH2_I2C_DATEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define EXT_LATCH2_I2C_DAT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define EXT_XT_CTL 0xbe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define EXT_XT_CAP16 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define EXT_XT_LINEARFB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define EXT_XT_PAL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define EXT_MEM_START 0xc0 /* ext start address 21 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define EXT_X_START 0xc5 /* ext->screen, 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EXT_X_END 0xc7 /* ext->screen, 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define EXT_Y_START 0xc9 /* ext->screen, 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EXT_Y_END 0xcb /* ext->screen, 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define EXT_COLOUR_COMPARE 0xce /* 24 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define EXT_VID_FIFO_CTL 0xd9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define EXT_VID_FMT 0xdb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define EXT_VID_FMT_RGB555 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define EXT_VID_FMT_RGB565 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define EXT_VID_FMT_RGB888_24 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define EXT_VID_FMT_RGB888_32 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define EXT_VID_FMT_RGB8 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define EXT_VID_FMT_RGB4444 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define EXT_VID_FMT_RGB8T 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define EXT_VID_FMT_YUV128 0x80 /* YUV data offset by 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define EXT_VID_DISP_CTL1 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 (if YUV128 set) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* disable vertical interpolation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define EXT_VID_FIFO_CTL1 0xdd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define EXT_VID_FIFO_CTL1_OE_HIGH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define EXT_VID_FIFO_CTL1_INTERLEAVE 0x04 /* enable interleaved memory read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define EXT_ROM_UCB4GH 0xe5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define EXT_ROM_UCB4GH_FREEZE 0x02 /* capture frozen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define EXT_ROM_UCB4GH_ODDFRAME 0x04 /* 1 = odd frame captured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define EXT_ROM_UCB4GH_1HL 0x08 /* first horizonal line after VGT falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define EXT_ROM_UCB4GH_ODD 0x10 /* odd frame indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define EXT_ROM_UCB4GH_INTSTAT 0x20 /* video interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define VFAC_CTL1 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define VFAC_CTL2 0xe9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define VFAC_CTL3 0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define VFAC_CTL3_CAP_LARGE_FIFO 0x01 /* large capture fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define VFAC_CTL3_CAP_INTERLACE 0x02 /* capture odd and even fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define VFAC_CTL3_CAP_HOLD_4NS 0x00 /* hold capture data for 4ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define VFAC_CTL3_CAP_HOLD_2NS 0x04 /* hold capture data for 2ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define VFAC_CTL3_CAP_HOLD_6NS 0x08 /* hold capture data for 6ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define VFAC_CTL3_CAP_HOLD_0NS 0x0c /* hold capture data for 0ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define VFAC_CTL3_CHROMAKEY 0x20 /* capture data will be chromakeyed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CAP_MEM_START 0xeb /* 18 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CAP_MAP_WIDTH 0xed /* high 6 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CAP_PITCH 0xee /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CAP_CTL_MISC 0xef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CAP_CTL_MISC_HDIV 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CAP_CTL_MISC_HDIV4 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CAP_CTL_MISC_ODDEVEN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CAP_CTL_MISC_HSYNCDIV2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CAP_CTL_MISC_SYNCTZHIGH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CAP_CTL_MISC_SYNCTZOR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CAP_CTL_MISC_DISPUSED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define REG_BANK 0xfa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define REG_BANK_X 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define REG_BANK_Y 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define REG_BANK_W 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define REG_BANK_T 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define REG_BANK_J 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define REG_BANK_K 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Bus-master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define BM_VID_ADDR_LOW 0xbc040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define BM_VID_ADDR_HIGH 0xbc044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define BM_ADDRESS_LOW 0xbc080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define BM_ADDRESS_HIGH 0xbc084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define BM_LENGTH 0xbc088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define BM_CONTROL 0xbc08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define BM_CONTROL_ENABLE 0x01 /* enable transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define BM_CONTROL_INIT 0x04 /* initialise status & count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define BM_COUNT 0xbc090 /* read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * TV registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TV_VBLANK_EVEN_START 0xbe43c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TV_VBLANK_EVEN_END 0xbe440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TV_VBLANK_ODD_START 0xbe444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TV_VBLANK_ODD_END 0xbe448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define TV_SYNC_YGAIN 0xbe44c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define TV_UV_GAIN 0xbe450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TV_PED_UVDET 0xbe454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define TV_UV_BURST_AMP 0xbe458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define TV_HSYNC_START 0xbe45c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define TV_HSYNC_END 0xbe460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define TV_Y_DELAY1 0xbe464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TV_Y_DELAY2 0xbe468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TV_UV_DELAY1 0xbe46c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TV_BURST_START 0xbe470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define TV_BURST_END 0xbe474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define TV_HBLANK_START 0xbe478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define TV_HBLANK_END 0xbe47c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define TV_PED_EVEN_START 0xbe480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TV_PED_EVEN_END 0xbe484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define TV_PED_ODD_START 0xbe488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define TV_PED_ODD_END 0xbe48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TV_VSYNC_EVEN_START 0xbe490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TV_VSYNC_EVEN_END 0xbe494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define TV_VSYNC_ODD_START 0xbe498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TV_VSYNC_ODD_END 0xbe49c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define TV_SCFL 0xbe4a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define TV_SCFH 0xbe4a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define TV_SCP 0xbe4a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define TV_DELAYBYPASS 0xbe4b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define TV_EQL_END 0xbe4bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TV_SERR_START 0xbe4c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define TV_SERR_END 0xbe4c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TV_VSYNC_VGA_HS 0xbe4e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TV_FLICK_XMIN 0xbe514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define TV_FLICK_XMAX 0xbe518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define TV_FLICK_YMIN 0xbe51c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define TV_FLICK_YMAX 0xbe520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Graphics Co-processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define CO_REG_CONTROL 0xbf011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CO_CTRL_BUSY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CO_CTRL_CMDFULL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CO_CTRL_FIFOEMPTY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CO_CTRL_READY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CO_REG_SRC_WIDTH 0xbf018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CO_REG_PIXFMT 0xbf01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CO_PIXFMT_32BPP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CO_PIXFMT_24BPP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CO_PIXFMT_16BPP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CO_PIXFMT_8BPP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CO_REG_FGMIX 0xbf048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CO_FG_MIX_ZERO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CO_FG_MIX_SRC_AND_DST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CO_FG_MIX_SRC_AND_NDST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CO_FG_MIX_SRC 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CO_FG_MIX_NSRC_AND_DST 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CO_FG_MIX_DST 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CO_FG_MIX_SRC_XOR_DST 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CO_FG_MIX_SRC_OR_DST 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CO_FG_MIX_NSRC_AND_NDST 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CO_FG_MIX_SRC_XOR_NDST 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CO_FG_MIX_NDST 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CO_FG_MIX_SRC_OR_NDST 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CO_FG_MIX_NSRC 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CO_FG_MIX_NSRC_OR_DST 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CO_FG_MIX_NSRC_OR_NDST 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CO_FG_MIX_ONES 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CO_REG_FGCOLOUR 0xbf058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CO_REG_BGCOLOUR 0xbf05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CO_REG_PIXWIDTH 0xbf060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CO_REG_PIXHEIGHT 0xbf062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CO_REG_X_PHASE 0xbf078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CO_REG_CMD_L 0xbf07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define CO_CMD_L_PATTERN_FGCOL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define CO_CMD_L_INC_LEFT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define CO_CMD_L_INC_UP 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define CO_REG_CMD_H 0xbf07e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define CO_CMD_H_BGSRCMAP 0x8000 /* otherwise bg colour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define CO_CMD_H_FGSRCMAP 0x2000 /* otherwise fg colour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define CO_CMD_H_BLITTER 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define CO_REG_SRC1_PTR 0xbf170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define CO_REG_SRC2_PTR 0xbf174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define CO_REG_DEST_PTR 0xbf178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define CO_REG_DEST_WIDTH 0xbf218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * Private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct cfb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct cyberpro_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned char __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) char __iomem *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) char dev_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int fb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * The following is a pointer to be passed into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * functions below. The modules outside the main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * cyber2000fb.c driver have no knowledge as to what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * is within this structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct cfb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define ID_IGA_1682 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define ID_CYBERPRO_2000 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define ID_CYBERPRO_2010 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define ID_CYBERPRO_5000 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Note! Writing to the Cyber20x0 registers from an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * routine is definitely a bad idea atm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int cyber2000fb_attach(struct cyberpro_info *info, int idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void cyber2000fb_detach(int idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) void cyber2000fb_enable_extregs(struct cfb_info *cfb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) void cyber2000fb_disable_extregs(struct cfb_info *cfb);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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