^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * controlfb.c -- frame buffer device for the PowerMac 'control' display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Created 12 July 1998 by Dan Jacobowitz <dan@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 Dan Jacobowitz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001 Takashi Oe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Mmap code by Michel Lanners <mlan@cpu.lu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Frame buffer structure from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * drivers/video/chipsfb.c -- frame buffer device for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Chips & Technologies 65550 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1998 Paul Mackerras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This file is derived from the Powermac "chips" driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 1997 Fabio Riccardi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * And from the frame buffer device for Open Firmware-initialized devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright (C) 1997 Geert Uytterhoeven.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Hardware information from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * control.c: Console support for PowerMac "control" display adaptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Copyright (C) 1996 Paul Mackerras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Updated to 2.5 framebuffer API by Ben Herrenschmidt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * and James Simmons <jsimmons@infradead.org>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/nvram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/adb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/cuda.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_PPC_PMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifdef CONFIG_BOOTX_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/btext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "macmodes.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "controlfb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #if !defined(CONFIG_PPC_PMAC) || !defined(CONFIG_PPC32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define invalid_vram_cache(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #undef in_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #undef out_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #undef in_le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #undef out_le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define in_8(addr) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define out_8(addr, val) (void)(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define in_le32(addr) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define out_le32(addr, val) (void)(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifndef pgprot_cached_wthru
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define pgprot_cached_wthru(prot) (prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void invalid_vram_cache(void __force *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) eieio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dcbf(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) eieio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dcbf(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct fb_par_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int vmode, cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int xres, yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int vxres, vyres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int xoffset, yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct control_regvals regvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned char ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DIRTY(z) ((x)->z != (y)->z)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int i, results;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) results = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) results &= !DIRTY(regvals.clock_params[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!results)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) results &= !DIRTY(regvals.regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!results)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) && !DIRTY(vxres) && !DIRTY(vyres));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline int VAR_MATCH(struct fb_var_screeninfo *x, struct fb_var_screeninfo *y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return (!DIRTY(bits_per_pixel) && !DIRTY(xres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) && !DIRTY(yres) && !DIRTY(xres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) && !DIRTY(yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) && !DIRTY_CMAP(red) && !DIRTY_CMAP(green) && !DIRTY_CMAP(blue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct fb_info_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct fb_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct fb_par_control par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct cmap_regs __iomem *cmap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long cmap_regs_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct control_regs __iomem *control_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long control_regs_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long control_regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __u8 __iomem *frame_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long frame_buffer_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long fb_orig_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long fb_orig_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int control_use_bank2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long total_vram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned char vram_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* control register access macro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /************************** Internal variables *******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct fb_info_control *control_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int default_vmode __initdata = VMODE_NVRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int default_cmode __initdata = CMODE_NVRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u_int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct fb_info_control *p =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) container_of(info, struct fb_info_control, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __u8 r, g, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (regno > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) r = red >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) g = green >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) b = blue >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) out_8(&p->cmap_regs->lut, r); /* send one color channel at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) out_8(&p->cmap_regs->lut, g); /* a time... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) out_8(&p->cmap_regs->lut, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (regno < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) switch (p->par.cmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case CMODE_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) p->pseudo_palette[regno] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (regno << 10) | (regno << 5) | regno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case CMODE_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) i = (regno << 8) | regno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) p->pseudo_palette[regno] = (i << 16) | i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /******************** End of controlfb_ops implementation ******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void set_control_clock(unsigned char *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_ADB_CUDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct adb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for (i = 0; i < 3; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0x50, i + 1, params[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) while (!req.complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cuda_poll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Set screen start address according to var offset values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline void set_screen_start(int xoffset, int yoffset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct fb_info_control *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct fb_par_control *par = &p->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) par->xoffset = xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) par->yoffset = yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) out_le32(CNTRL_REG(p,start_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) par->yoffset * par->pitch + (par->xoffset << par->cmode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RADACAL_WRITE(a,d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) out_8(&p->cmap_regs->addr, (a)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) out_8(&p->cmap_regs->dat, (d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Now how about actually saying, Make it so! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Some things in here probably don't need to be done each time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct control_regvals *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) volatile struct preg __iomem *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int i, cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (PAR_EQUAL(&p->par, par)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * check if only xoffset or yoffset differs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * this prevents flickers in typical VT switch case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (p->par.xoffset != par->xoffset ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) p->par.yoffset != par->yoffset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) set_screen_start(par->xoffset, par->yoffset, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) p->par = *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cmode = p->par.cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) r = &par->regvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Turn off display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) set_control_clock(r->clock_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) RADACAL_WRITE(0x20, r->radacal_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) RADACAL_WRITE(0x10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) RADACAL_WRITE(0x11, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) rp = &p->control_regs->vswin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (i = 0; i < 16; ++i, ++rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) out_le32(&rp->r, r->regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) out_le32(CNTRL_REG(p,pitch), par->pitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) out_le32(CNTRL_REG(p,mode), r->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) out_le32(CNTRL_REG(p,vram_attr), p->vram_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) + (par->xoffset << cmode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) out_le32(CNTRL_REG(p,rfrcnt), 0x1e5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) out_le32(CNTRL_REG(p,intr_ena), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Turn on display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) out_le32(CNTRL_REG(p,ctrl), par->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #ifdef CONFIG_BOOTX_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) btext_update_display(p->frame_buffer_phys + CTRLFB_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) p->par.xres, p->par.yres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) p->par.pitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif /* CONFIG_BOOTX_TEXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Work out which banks of VRAM we have installed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* danj: I guess the card just ignores writes to nonexistant VRAM... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void __init find_vram_size(struct fb_info_control *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int bank1, bank2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Set VRAM in 2MB (bank 1) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * VRAM Bank 2 will be accessible through offset 0x600000 if present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * and VRAM Bank 1 will not respond at that offset even if present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) out_le32(CNTRL_REG(p,vram_attr), 0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) out_8(&p->frame_buffer[0x600000], 0xb3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) out_8(&p->frame_buffer[0x600001], 0x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) invalid_vram_cache(&p->frame_buffer[0x600000]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) && (in_8(&p->frame_buffer[0x600001]) == 0x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Set VRAM in 2MB (bank 2) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * VRAM Bank 1 will be accessible through offset 0x000000 if present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * and VRAM Bank 2 will not respond at that offset even if present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) out_le32(CNTRL_REG(p,vram_attr), 0x39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) out_8(&p->frame_buffer[0], 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) out_8(&p->frame_buffer[1], 0xc7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) invalid_vram_cache(&p->frame_buffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bank1 = (in_8(&p->frame_buffer[0]) == 0x5a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) && (in_8(&p->frame_buffer[1]) == 0xc7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (bank2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!bank1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * vram bank 2 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) p->control_use_bank2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) p->vram_attr = 0x39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) p->frame_buffer += 0x600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) p->frame_buffer_phys += 0x600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * 4 MB vram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) p->vram_attr = 0x51;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * vram bank 1 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) p->vram_attr = 0x31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) p->total_vram = (bank1 + bank2) * 0x200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) printk(KERN_INFO "controlfb: VRAM Total = %dMB "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "(%dMB @ bank 1, %dMB @ bank 2)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) (bank1 + bank2) << 1, bank1 << 1, bank2 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Get the monitor sense value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Note that this can be called before calibrate_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * so we can't use udelay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int read_control_sense(struct fb_info_control *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) __delay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __delay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* drive each sense line low in turn and collect the other 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __delay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __delay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) __delay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /********************** Various translation functions **********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CONTROL_PIXCLOCK_BASE 256016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * calculate the clock paramaters to be sent to CUDA according to given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * pixclock in pico second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int calc_clock_params(unsigned long clk, unsigned char *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned long p0, p1, p2, k, l, m, n, min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (clk > (CONTROL_PIXCLOCK_BASE << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) l = clk << p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) p0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) p1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (k = 1, min = l; k < 32; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned long rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) m = CONTROL_PIXCLOCK_BASE * k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) n = m / l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rem = m % l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (n && (n < 128) && rem < min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) p0 = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) p1 = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) min = rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!p0 || !p1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) param[0] = p0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) param[1] = p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) param[2] = p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * This routine takes a user-supplied var, and picks the best vmode/cmode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * from it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int control_var_to_par(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct fb_par_control *par, const struct fb_info *fb_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int cmode, piped_diff, hstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned long pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct fb_info_control *p =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) container_of(fb_info, struct fb_info_control, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct control_regvals *r = &par->regvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) switch (var->bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) par->cmode = CMODE_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (p->total_vram > 0x200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) r->mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) r->radacal_ctrl = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) piped_diff = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) r->mode = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) r->radacal_ctrl = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) piped_diff = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) par->cmode = CMODE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (p->total_vram > 0x200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) r->mode = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) r->radacal_ctrl = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) piped_diff = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) r->mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) r->radacal_ctrl = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) piped_diff = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) par->cmode = CMODE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (p->total_vram > 0x200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) r->mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) r->radacal_ctrl = 0x28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) r->mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) r->radacal_ctrl = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) piped_diff = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * adjust xres and vxres so that the corresponding memory widths are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * 32-byte aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) hstep = 31 >> par->cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) par->xres = (var->xres + hstep) & ~hstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) par->vxres = (var->xres_virtual + hstep) & ~hstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) par->xoffset = (var->xoffset + hstep) & ~hstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (par->vxres < par->xres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) par->vxres = par->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) par->pitch = par->vxres << par->cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) par->yres = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) par->vyres = var->yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) par->yoffset = var->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (par->vyres < par->yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) par->vyres = par->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) par->sync = var->sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (par->xoffset + par->xres > par->vxres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) par->xoffset = par->vxres - par->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (par->yoffset + par->yres > par->vyres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) par->yoffset = par->vyres - par->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) var->pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (calc_clock_params(pixclock, r->clock_params))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) hperiod = ((var->left_margin + par->xres + var->right_margin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) + var->hsync_len) >> 1) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) hssync = hperiod + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) hsblank = hssync - (var->right_margin >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) hesync = (var->hsync_len >> 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) heblank = (var->left_margin >> 1) + hesync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) piped = heblank - piped_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) heq = var->hsync_len >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hlfln = (hperiod+2) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hserr = hssync-hesync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) vperiod = (var->vsync_len + var->lower_margin + par->yres
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) + var->upper_margin) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) vssync = vperiod - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) vesync = (var->vsync_len << 1) - vperiod + vssync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) veblank = (var->upper_margin << 1) + vesync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) vsblank = vssync - (var->lower_margin << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) vswin = (vsblank+vssync) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) vewin = (vesync+veblank) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) r->regs[0] = vswin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) r->regs[1] = vsblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) r->regs[2] = veblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) r->regs[3] = vewin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) r->regs[4] = vesync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) r->regs[5] = vssync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) r->regs[6] = vperiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) r->regs[7] = piped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) r->regs[8] = hperiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) r->regs[9] = hsblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) r->regs[10] = heblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) r->regs[11] = hesync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) r->regs[12] = hssync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) r->regs[13] = heq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) r->regs[14] = hlfln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) r->regs[15] = hserr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (par->xres >= 1280 && par->cmode >= CMODE_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) par->ctrl = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) par->ctrl = 0x3b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (mac_var_to_vmode(var, &par->vmode, &cmode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) par->vmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Convert hardware data in par to an fb_var_screeninfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct control_regints *rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) rv = (struct control_regints *) par->regvals.regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) memset(var, 0, sizeof(*var));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) var->xres = par->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) var->yres = par->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) var->xres_virtual = par->vxres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) var->yres_virtual = par->vyres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) var->xoffset = par->xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) var->yoffset = par->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) switch(par->cmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case CMODE_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) var->bits_per_pixel = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case CMODE_16: /* RGB 555 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) var->bits_per_pixel = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) var->red.offset = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) var->red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) var->green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) var->green.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case CMODE_32: /* RGB 888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) var->bits_per_pixel = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) var->red.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) var->transp.offset = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) var->transp.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) var->height = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) var->width = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) var->vmode = FB_VMODE_NONINTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) var->left_margin = (rv->heblank - rv->hesync) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) var->right_margin = (rv->hssync - rv->hsblank) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) var->upper_margin = (rv->veblank - rv->vesync) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) var->lower_margin = (rv->vssync - rv->vsblank) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) var->sync = par->sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * 10^12 * clock_params[0] / (3906400 * clock_params[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * * 2^clock_params[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * (10^12 * clock_params[0] / (3906400 * clock_params[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * >> clock_params[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) var->pixclock /= par->regvals.clock_params[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) var->pixclock >>= par->regvals.clock_params[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /******************** The functions for controlfb_ops ********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Checks a var structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct fb_par_control par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) err = control_var_to_par(var, &par, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) control_par_to_var(&par, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * Applies current var to display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int controlfb_set_par (struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct fb_info_control *p =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) container_of(info, struct fb_info_control, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct fb_par_control par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if((err = control_var_to_par(&info->var, &par, info))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) printk (KERN_ERR "controlfb_set_par: error calling"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) " control_var_to_par: %d.\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) control_set_hardware(p, &par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) info->fix.visual = (p->par.cmode == CMODE_8) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) info->fix.line_length = p->par.pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) info->fix.xpanstep = 32 >> p->par.cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) info->fix.ypanstep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int controlfb_pan_display(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned int xoffset, hstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct fb_info_control *p =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) container_of(info, struct fb_info_control, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct fb_par_control *par = &p->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * make sure start addr will be 32-byte aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) hstep = 0x1f >> par->cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) xoffset = (var->xoffset + hstep) & ~hstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (xoffset+par->xres > par->vxres ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) var->yoffset+par->yres > par->vyres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) set_screen_start(xoffset, var->yoffset, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int controlfb_blank(int blank_mode, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct fb_info_control __maybe_unused *p =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) container_of(info, struct fb_info_control, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ctrl = in_le32(CNTRL_REG(p, ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (blank_mode > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) switch (blank_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) case FB_BLANK_VSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ctrl &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case FB_BLANK_HSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ctrl &= ~0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case FB_BLANK_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ctrl &= ~0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case FB_BLANK_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ctrl |= 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ctrl &= ~0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ctrl |= 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) out_le32(CNTRL_REG(p,ctrl), ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Private mmap since we want to have a different caching on the framebuffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * for controlfb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * Note there's no locking in here; it's done in fb_mmap() in fbmem.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int controlfb_mmap(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned long mmio_pgoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) unsigned long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) start = info->fix.smem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) len = info->fix.smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mmio_pgoff = PAGE_ALIGN((start & ~PAGE_MASK) + len) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (vma->vm_pgoff >= mmio_pgoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (info->var.accel_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) vma->vm_pgoff -= mmio_pgoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) start = info->fix.mmio_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) len = info->fix.mmio_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* framebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return vm_iomap_memory(vma, start, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const struct fb_ops controlfb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .fb_check_var = controlfb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .fb_set_par = controlfb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .fb_setcolreg = controlfb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .fb_pan_display = controlfb_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .fb_blank = controlfb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .fb_mmap = controlfb_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * Set misc info vars for this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static void __init control_init_info(struct fb_info *info, struct fb_info_control *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Fill fb_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) info->par = &p->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) info->fbops = &controlfb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) info->pseudo_palette = p->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) info->screen_base = p->frame_buffer + CTRLFB_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) fb_alloc_cmap(&info->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Fill fix common fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) strcpy(info->fix.id, "control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) info->fix.mmio_start = p->control_regs_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) info->fix.mmio_len = sizeof(struct control_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) info->fix.type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) info->fix.smem_len = p->total_vram - CTRLFB_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) info->fix.ywrapstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) info->fix.type_aux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) info->fix.accel = FB_ACCEL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Parse user specified options (`video=controlfb:')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static void __init control_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) char *this_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) while ((this_opt = strsep(&options, ",")) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (!strncmp(this_opt, "vmode:", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int vmode = simple_strtoul(this_opt+6, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (vmode > 0 && vmode <= VMODE_MAX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) control_mac_modes[vmode - 1].m[1] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) default_vmode = vmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) } else if (!strncmp(this_opt, "cmode:", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int depth = simple_strtoul(this_opt+6, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) switch (depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case CMODE_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case CMODE_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case CMODE_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) default_cmode = depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) default_cmode = CMODE_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) default_cmode = CMODE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) default_cmode = CMODE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * finish off the driver initialization and register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int __init init_control(struct fb_info_control *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int full, sense, vmode, cmode, vyres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct fb_var_screeninfo var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) printk(KERN_INFO "controlfb: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) full = p->total_vram == 0x400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* Try to pick a video mode out of NVRAM if we have one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) cmode = default_cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (IS_REACHABLE(CONFIG_NVRAM) && cmode == CMODE_NVRAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) cmode = nvram_read_byte(NV_CMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (cmode < CMODE_8 || cmode > CMODE_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) cmode = CMODE_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) vmode = default_vmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (IS_REACHABLE(CONFIG_NVRAM) && vmode == VMODE_NVRAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) vmode = nvram_read_byte(NV_VMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (vmode < 1 || vmode > VMODE_MAX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) control_mac_modes[vmode - 1].m[full] < cmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) sense = read_control_sense(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) printk(KERN_CONT "Monitor sense value = 0x%x, ", sense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) vmode = mac_map_monitor_sense(sense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (control_mac_modes[vmode - 1].m[full] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) vmode = VMODE_640_480_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) cmode = min(cmode, control_mac_modes[vmode - 1].m[full]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* Initialize info structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) control_init_info(&p->info, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* Setup default var */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* This shouldn't happen! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) try_again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) vmode = VMODE_640_480_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) cmode = CMODE_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) printk(KERN_INFO "controlfb: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) printk("using video mode %d and color mode %d.\n", vmode, cmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (vyres > var.yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) var.yres_virtual = vyres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Apply default var */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) var.activate = FB_ACTIVATE_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) rc = fb_set_var(&p->info, &var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto try_again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Register with fbdev layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (register_framebuffer(&p->info) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) fb_info(&p->info, "control display adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static void control_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct fb_info_control *p = control_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (p->cmap_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) iounmap(p->cmap_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (p->control_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) iounmap(p->control_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (p->frame_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (p->control_use_bank2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) p->frame_buffer -= 0x600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) iounmap(p->frame_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (p->cmap_regs_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) release_mem_region(p->cmap_regs_phys, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (p->control_regs_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) release_mem_region(p->control_regs_phys, p->control_regs_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (p->fb_orig_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) release_mem_region(p->fb_orig_base, p->fb_orig_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * find "control" and initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int __init control_of_init(struct device_node *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct fb_info_control *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct resource fb_res, reg_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (control_fb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) printk(KERN_ERR "controlfb: only one control is supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (of_pci_address_to_resource(dp, 2, &fb_res) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) of_pci_address_to_resource(dp, 1, ®_res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) printk(KERN_ERR "can't get 2 addresses for control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) p = kzalloc(sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) control_fb = p; /* save it for cleanups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* Map in frame buffer and registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) p->fb_orig_base = fb_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) p->fb_orig_size = resource_size(&fb_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* use the big-endian aperture (??) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) p->frame_buffer_phys = fb_res.start + 0x800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) p->control_regs_phys = reg_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) p->control_regs_size = resource_size(®_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!p->fb_orig_base ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) !request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) p->fb_orig_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* map at most 8MB for the frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) p->frame_buffer = ioremap_wt(p->frame_buffer_phys, 0x800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!p->control_regs_phys ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) !request_mem_region(p->control_regs_phys, p->control_regs_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "controlfb regs")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) p->control_regs_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) p->cmap_regs_phys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (!p->cmap_regs || !p->control_regs || !p->frame_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) find_vram_size(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!p->total_vram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (init_control(p) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) control_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int __init control_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) char *option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (fb_get_options("controlfb", &option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) control_setup(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dp = of_find_node_by_name(NULL, "control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (dp && !control_of_init(dp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) of_node_put(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) device_initcall(control_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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