^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _CARMINEFB_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _CARMINEFB_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define CARMINE_GRAPH_REG (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define CARMINE_DISP0_REG (0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define CARMINE_DISP1_REG (0x00140000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CARMINE_WB_REG (0x00180000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CARMINE_DCTL_REG (0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CARMINE_CTL_REG (0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CARMINE_WINDOW_MODE (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CARMINE_EXTEND_MODE (CARMINE_WINDOW_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) CARMINE_OVERLAY_EXT_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CARMINE_L0E (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CARMINE_L2E (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CARMINE_DEN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CARMINE_DCTL_REG_MODE_ADD (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CARMINE_DCTL_REG_SETTIME1_EMODE (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CARMINE_DCTL_REG_REFRESH_SETTIME2 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CARMINE_DCTL_REG_RSV0_STATES (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CARMINE_DCTL_REG_RSV2_RSV1 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CARMINE_DCTL_REG_DDRIF2_DDRIF1 (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CARMINE_DCTL_REG_IOCONT1_IOCONT0 (0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CARMINE_DCTL_REG_STATES_MASK (0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CARMINE_DCTL_INIT_WAIT_INTERVAL (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CARMINE_DCTL_INIT_WAIT_LIMIT (5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CARMINE_WB_REG_WBM_DEFAULT (0x0001c020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CARMINE_DISP_REG_L0RM (0x1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CARMINE_DISP_REG_L0PX (0x1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CARMINE_DISP_REG_L0PY (0x1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CARMINE_DISP_REG_L2RM (0x18A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CARMINE_DISP_REG_L2PX (0x18A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CARMINE_DISP_REG_L2PY (0x18A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CARMINE_DISP_REG_L3RM (0x18B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CARMINE_DISP_REG_L3PX (0x18B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CARMINE_DISP_REG_L3PY (0x18B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CARMINE_DISP_REG_L4RM (0x18C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CARMINE_DISP_REG_L4PX (0x18C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CARMINE_DISP_REG_L4PY (0x18C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CARMINE_DISP_REG_L5RM (0x18D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CARMINE_DISP_REG_L5PX (0x18D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CARMINE_DISP_REG_L5PY (0x18D8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CARMINE_DISP_REG_L6RM (0x1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CARMINE_DISP_REG_L6PX (0x1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CARMINE_DISP_REG_L6PY (0x192C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CARMINE_DISP_REG_L7RM (0x1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CARMINE_DISP_REG_L7PX (0x1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CARMINE_DISP_REG_L7PY (0x196C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CARMINE_WB_REG_WBM (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CARMINE_DISP_HTP_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CARMINE_DISP_HDB_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CARMINE_DISP_HSW_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CARMINE_DISP_VSW_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CARMINE_DISP_VTR_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CARMINE_DISP_VDP_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CARMINE_CURSOR_CUTZ_MASK (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CARMINE_CURSOR0_PRIORITY_MASK (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CARMINE_CURSOR1_PRIORITY_MASK (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CARMINE_DISP_WIDTH_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CARMINE_DISP_WIN_H_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CARMINE_DISP_REG_H_TOTAL (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CARMINE_DISP_REG_H_PERIOD (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CARMINE_DISP_REG_V_H_W_H_POS (0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CARMINE_DISP_REG_V_TOTAL (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CARMINE_DISP_REG_V_PERIOD_POS (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CARMINE_DISP_REG_L0_MODE_W_H (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CARMINE_DISP_REG_L0_ORG_ADR (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CARMINE_DISP_REG_L0_DISP_ADR (0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CARMINE_DISP_REG_L0_DISP_POS (0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CARMINE_DISP_REG_L1_WIDTH (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CARMINE_DISP_REG_L1_ORG_ADR (0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CARMINE_DISP_REG_L2_MODE_W_H (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CARMINE_DISP_REG_L2_ORG_ADR1 (0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CARMINE_DISP_REG_L2_DISP_ADR1 (0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CARMINE_DISP_REG_L2_DISP_POS (0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CARMINE_DISP_REG_L3_MODE_W_H (0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CARMINE_DISP_REG_L3_ORG_ADR1 (0x005C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CARMINE_DISP_REG_L3_DISP_ADR1 (0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CARMINE_DISP_REG_L3_DISP_POS (0x006C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CARMINE_DISP_REG_L4_MODE_W_H (0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CARMINE_DISP_REG_L4_ORG_ADR1 (0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CARMINE_DISP_REG_L4_DISP_ADR1 (0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CARMINE_DISP_REG_L4_DISP_POS (0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CARMINE_DISP_REG_L5_MODE_W_H (0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CARMINE_DISP_REG_L5_ORG_ADR1 (0x008C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CARMINE_DISP_REG_L5_DISP_ADR1 (0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CARMINE_DISP_REG_L5_DISP_POS (0x009C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CARMINE_DISP_REG_CURSOR_MODE (0x00A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CARMINE_DISP_REG_CUR1_POS (0x00A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CARMINE_DISP_REG_CUR2_POS (0x00B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CARMINE_DISP_REG_C_TRANS (0x00BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CARMINE_DISP_REG_MLMR_TRANS (0x00C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CARMINE_DISP_REG_L0_EXT_MODE (0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CARMINE_DISP_REG_L0_WIN_POS (0x0114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CARMINE_DISP_REG_L0_WIN_SIZE (0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CARMINE_DISP_REG_L1_EXT_MODE (0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CARMINE_DISP_REG_L1_WIN_POS (0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CARMINE_DISP_REG_L1_WIN_SIZE (0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CARMINE_DISP_REG_L2_EXT_MODE (0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CARMINE_DISP_REG_L2_WIN_POS (0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CARMINE_DISP_REG_L2_WIN_SIZE (0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CARMINE_DISP_REG_L3_EXT_MODE (0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CARMINE_DISP_REG_L3_WIN_POS (0x0144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CARMINE_DISP_REG_L3_WIN_SIZE (0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CARMINE_DISP_REG_L4_EXT_MODE (0x0150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CARMINE_DISP_REG_L4_WIN_POS (0x0154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CARMINE_DISP_REG_L4_WIN_SIZE (0x0158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CARMINE_DISP_REG_L5_EXT_MODE (0x0160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CARMINE_DISP_REG_L5_WIN_POS (0x0164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CARMINE_DISP_REG_L5_WIN_SIZE (0x0168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CARMINE_DISP_REG_L6_EXT_MODE (0x1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CARMINE_DISP_REG_L6_WIN_POS (0x191c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CARMINE_DISP_REG_L6_WIN_SIZE (0x1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CARMINE_DISP_REG_L7_EXT_MODE (0x1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CARMINE_DISP_REG_L7_WIN_POS (0x195c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CARMINE_DISP_REG_L7_WIN_SIZE (0x1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CARMINE_DISP_REG_BLEND_MODE_L0 (0x00B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CARMINE_DISP_REG_BLEND_MODE_L1 (0x0188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CARMINE_DISP_REG_BLEND_MODE_L2 (0x018C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CARMINE_DISP_REG_BLEND_MODE_L3 (0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CARMINE_DISP_REG_BLEND_MODE_L4 (0x0194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CARMINE_DISP_REG_BLEND_MODE_L5 (0x0198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CARMINE_DISP_REG_BLEND_MODE_L6 (0x1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CARMINE_DISP_REG_BLEND_MODE_L7 (0x1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CARMINE_DISP_REG_L0_TRANS (0x01A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CARMINE_DISP_REG_L1_TRANS (0x01A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CARMINE_DISP_REG_L2_TRANS (0x01A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CARMINE_DISP_REG_L3_TRANS (0x01AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CARMINE_DISP_REG_L4_TRANS (0x01B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CARMINE_DISP_REG_L5_TRANS (0x01B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CARMINE_DISP_REG_L6_TRANS (0x1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CARMINE_DISP_REG_L7_TRANS (0x199c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CARMINE_EXTEND_MODE_MASK (0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CARMINE_DISP_DCM_MASK (0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CARMINE_DISP_REG_DCM1 (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CARMINE_DISP_WIDTH_UNIT (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CARMINE_DISP_REG_L6_MODE_W_H (0x1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CARMINE_DISP_REG_L6_ORG_ADR1 (0x1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CARMINE_DISP_REG_L6_DISP_ADR0 (0x1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CARMINE_DISP_REG_L6_DISP_POS (0x1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CARMINE_DISP_REG_L7_MODE_W_H (0x1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CARMINE_DISP_REG_L7_ORG_ADR1 (0x1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CARMINE_DISP_REG_L7_DISP_ADR0 (0x1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CARMINE_DISP_REG_L7_DISP_POS (0x1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CARMINE_CTL_REG_CLOCK_ENABLE (0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CARMINE_CTL_REG_SOFTWARE_RESET (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CARMINE_CTL_REG_IST_MASK_ALL (0x07FFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CARMINE_GRAPH_REG_VRINTM (0x00028064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CARMINE_GRAPH_REG_VRERRM (0x0002806C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CARMINE_GRAPH_REG_DC_OFFSET_PX (0x0004005C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CARMINE_GRAPH_REG_DC_OFFSET_PY (0x00040060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CARMINE_GRAPH_REG_DC_OFFSET_LX (0x00040064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CARMINE_GRAPH_REG_DC_OFFSET_LY (0x00040068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CARMINE_GRAPH_REG_DC_OFFSET_TX (0x0004006C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CARMINE_GRAPH_REG_DC_OFFSET_TY (0x00040070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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