Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef CARMINE_CARMINE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define CARMINE_CARMINE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define CARMINE_MEMORY_BAR	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define CARMINE_CONFIG_BAR	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define MAX_DISPLAY	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define CARMINE_DISPLAY_MEM	(800 * 600 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CARMINE_TOTAL_DIPLAY_MEM	(CARMINE_DISPLAY_MEM * MAX_DISPLAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CARMINE_USE_DISPLAY0	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CARMINE_USE_DISPLAY1	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * This values work on the eval card. Custom boards may use different timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * here an example :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* DRAM initialization values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_FB_CARMINE_DRAM_EVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CARMINE_DFLT_IP_CLOCK_ENABLE		(0x03ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CARMINE_DFLT_IP_DCTL_ADD		(0x05c3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CARMINE_DFLT_IP_DCTL_MODE		(0x0121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CARMINE_DFLT_IP_DCTL_EMODE		(0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CARMINE_DFLT_IP_DCTL_SET_TIME1		(0x4749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CARMINE_DFLT_IP_DCTL_SET_TIME2		(0x2a22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CARMINE_DFLT_IP_DCTL_REFRESH		(0x0042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CARMINE_DFLT_IP_DCTL_STATES		(0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CARMINE_DFLT_IP_DCTL_RESERVE0		(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH		(0x000f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CARMINE_DFLT_IP_DCTL_RESERVE2		(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CARMINE_DFLT_IP_DCTL_DDRIF1		(0x6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CARMINE_DFLT_IP_DCTL_DDRIF2		(0x0055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST	(0x0021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST	(0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CARMINE_DFLT_IP_DCTL_IO_CONT0		(0x0555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CARMINE_DFLT_IP_DCTL_IO_CONT1		(0x0555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CARMINE_DCTL_DLL_RESET			(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifdef CONFIG_CARMINE_DRAM_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CARMINE_DFLT_IP_CLOCK_ENABLE		(0x03ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CARMINE_DFLT_IP_DCTL_ADD		(0x03b2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CARMINE_DFLT_IP_DCTL_MODE		(0x0161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CARMINE_DFLT_IP_DCTL_EMODE		(0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CARMINE_DFLT_IP_DCTL_SET_TIME1		(0x2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CARMINE_DFLT_IP_DCTL_SET_TIME2		(0x1a09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CARMINE_DFLT_IP_DCTL_REFRESH		(0x00fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CARMINE_DFLT_IP_DCTL_STATES		(0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CARMINE_DFLT_IP_DCTL_RESERVE0		(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH		(0x000f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CARMINE_DFLT_IP_DCTL_RESERVE2		(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CARMINE_DFLT_IP_DCTL_DDRIF1		(0x0646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CARMINE_DFLT_IP_DCTL_DDRIF2		(0x55aa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST	(0x0061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST	(0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CARMINE_DFLT_IP_DCTL_IO_CONT0		(0x0555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CARMINE_DFLT_IP_DCTL_IO_CONT1		(0x0555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CARMINE_DCTL_DLL_RESET			(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif