^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Frame buffer driver for the Carmine GPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The driver configures the GPU as follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * - FB0 is display 0 with unique memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - FB1 is display 1 with unique memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - both display use 32 bit colors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "carminefb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "carminefb_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #error "The endianness of the target host has not been defined."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * The initial video mode can be supplied via two different ways:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * - as a string that is passed to fb_find_mode() (module option fb_mode_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - as an integer that picks the video mode from carmine_modedb[] (module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * option fb_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * If nothing is used than the initial video mode will be the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * CARMINEFB_DEFAULT_VIDEO_MODE member of the carmine_modedb[].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CARMINEFB_DEFAULT_VIDEO_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static unsigned int fb_mode = CARMINEFB_DEFAULT_VIDEO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param(fb_mode, uint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(fb_mode, "Initial video mode as integer.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static char *fb_mode_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) module_param(fb_mode_str, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_PARM_DESC(fb_mode_str, "Initial video mode in characters.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Carminefb displays:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 0b000 None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 0b001 Display 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 0b010 Display 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int fb_displays = CARMINE_USE_DISPLAY0 | CARMINE_USE_DISPLAY1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) module_param(fb_displays, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_PARM_DESC(fb_displays, "Bit mode, which displays are used");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct carmine_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *v_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *screen_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct fb_info *fb[MAX_DISPLAY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct carmine_resolution {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 htp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 hsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 hdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 vtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 vsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 vsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 vdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 disp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct carmine_fb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *display_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void __iomem *screen_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 smem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct carmine_resolution *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct fb_fix_screeninfo carminefb_fix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .id = "Carmine",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .visual = FB_VISUAL_TRUECOLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .accel = FB_ACCEL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct fb_videomode carmine_modedb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "640x480",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "800x600",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .yres = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct carmine_resolution car_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* 640x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .htp = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .hsp = 672,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .hsw = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .hdp = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .vtr = 525,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .vsp = 490,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .vsw = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .vdp = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .disp_mode = 0x1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 800x600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .htp = 1060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .hsp = 864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .hsw = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .hdp = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .vtr = 628,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .vsp = 601,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .vsw = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .vdp = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .disp_mode = 0x0d00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int carmine_find_mode(const struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) for (i = 0; i < ARRAY_SIZE(car_modes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (car_modes[i].hdp == var->xres &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) car_modes[i].vdp == var->yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void c_set_disp_reg(const struct carmine_fb *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(val, par->display_reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u32 c_get_disp_reg(const struct carmine_fb *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return readl(par->display_reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void c_set_hw_reg(const struct carmine_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(val, hw->v_regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static u32 c_get_hw_reg(const struct carmine_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return readl(hw->v_regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int carmine_setcolreg(unsigned regno, unsigned red, unsigned green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned blue, unsigned transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (regno >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) red >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) green >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) blue >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) transp >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ((__be32 *)info->pseudo_palette)[regno] = cpu_to_be32(transp << 24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) red << 0 | green << 8 | blue << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int carmine_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = carmine_find_mode(var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (var->grayscale || var->rotate || var->nonstd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) var->xres_virtual = var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) var->yres_virtual = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) var->bits_per_pixel = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) var->transp.offset = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) var->red.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) var->blue.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) var->transp.offset = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) var->red.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) var->transp.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) var->red.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) var->green.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) var->blue.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) var->transp.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void carmine_init_display_param(struct carmine_fb *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 soffset = par->smem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) c_set_disp_reg(par, CARMINE_DISP_REG_C_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) c_set_disp_reg(par, CARMINE_DISP_REG_MLMR_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) c_set_disp_reg(par, CARMINE_DISP_REG_CURSOR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CARMINE_CURSOR0_PRIORITY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CARMINE_CURSOR1_PRIORITY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CARMINE_CURSOR_CUTZ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Set default cursor position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) c_set_disp_reg(par, CARMINE_DISP_REG_CUR1_POS, 0 << 16 | 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) c_set_disp_reg(par, CARMINE_DISP_REG_CUR2_POS, 0 << 16 | 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Set default display mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) c_set_disp_reg(par, CARMINE_DISP_REG_L0_EXT_MODE, CARMINE_WINDOW_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CARMINE_EXT_CMODE_DIRECT24_RGBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) c_set_disp_reg(par, CARMINE_DISP_REG_L1_EXT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CARMINE_EXT_CMODE_DIRECT24_RGBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) c_set_disp_reg(par, CARMINE_DISP_REG_L2_EXT_MODE, CARMINE_EXTEND_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CARMINE_EXT_CMODE_DIRECT24_RGBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) c_set_disp_reg(par, CARMINE_DISP_REG_L3_EXT_MODE, CARMINE_EXTEND_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CARMINE_EXT_CMODE_DIRECT24_RGBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) c_set_disp_reg(par, CARMINE_DISP_REG_L4_EXT_MODE, CARMINE_EXTEND_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) CARMINE_EXT_CMODE_DIRECT24_RGBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) c_set_disp_reg(par, CARMINE_DISP_REG_L5_EXT_MODE, CARMINE_EXTEND_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) CARMINE_EXT_CMODE_DIRECT24_RGBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) c_set_disp_reg(par, CARMINE_DISP_REG_L6_EXT_MODE, CARMINE_EXTEND_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CARMINE_EXT_CMODE_DIRECT24_RGBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) c_set_disp_reg(par, CARMINE_DISP_REG_L7_EXT_MODE, CARMINE_EXTEND_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CARMINE_EXT_CMODE_DIRECT24_RGBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Set default frame size to layer mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) width = par->res->hdp * 4 / CARMINE_DISP_WIDTH_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) width = width << CARMINE_DISP_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) height = par->res->vdp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) param = width | height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) c_set_disp_reg(par, CARMINE_DISP_REG_L0_MODE_W_H, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIDTH, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) c_set_disp_reg(par, CARMINE_DISP_REG_L2_MODE_W_H, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) c_set_disp_reg(par, CARMINE_DISP_REG_L3_MODE_W_H, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) c_set_disp_reg(par, CARMINE_DISP_REG_L4_MODE_W_H, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) c_set_disp_reg(par, CARMINE_DISP_REG_L5_MODE_W_H, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) c_set_disp_reg(par, CARMINE_DISP_REG_L6_MODE_W_H, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) c_set_disp_reg(par, CARMINE_DISP_REG_L7_MODE_W_H, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Set default pos and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) window_size = (par->res->vdp - 1) << CARMINE_DISP_WIN_H_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) window_size |= par->res->hdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) c_set_disp_reg(par, CARMINE_DISP_REG_L0_WIN_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) c_set_disp_reg(par, CARMINE_DISP_REG_L0_WIN_SIZE, window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIN_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIN_SIZE, window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) c_set_disp_reg(par, CARMINE_DISP_REG_L2_WIN_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) c_set_disp_reg(par, CARMINE_DISP_REG_L2_WIN_SIZE, window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) c_set_disp_reg(par, CARMINE_DISP_REG_L3_WIN_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) c_set_disp_reg(par, CARMINE_DISP_REG_L3_WIN_SIZE, window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) c_set_disp_reg(par, CARMINE_DISP_REG_L4_WIN_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) c_set_disp_reg(par, CARMINE_DISP_REG_L4_WIN_SIZE, window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) c_set_disp_reg(par, CARMINE_DISP_REG_L5_WIN_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) c_set_disp_reg(par, CARMINE_DISP_REG_L5_WIN_SIZE, window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) c_set_disp_reg(par, CARMINE_DISP_REG_L6_WIN_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) c_set_disp_reg(par, CARMINE_DISP_REG_L6_WIN_SIZE, window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) c_set_disp_reg(par, CARMINE_DISP_REG_L7_WIN_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) c_set_disp_reg(par, CARMINE_DISP_REG_L7_WIN_SIZE, window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Set default origin address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) c_set_disp_reg(par, CARMINE_DISP_REG_L0_ORG_ADR, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) c_set_disp_reg(par, CARMINE_DISP_REG_L1_ORG_ADR, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) c_set_disp_reg(par, CARMINE_DISP_REG_L2_ORG_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) c_set_disp_reg(par, CARMINE_DISP_REG_L3_ORG_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) c_set_disp_reg(par, CARMINE_DISP_REG_L4_ORG_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) c_set_disp_reg(par, CARMINE_DISP_REG_L5_ORG_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) c_set_disp_reg(par, CARMINE_DISP_REG_L6_ORG_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) c_set_disp_reg(par, CARMINE_DISP_REG_L7_ORG_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Set default display address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) c_set_disp_reg(par, CARMINE_DISP_REG_L0_DISP_ADR, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) c_set_disp_reg(par, CARMINE_DISP_REG_L2_DISP_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) c_set_disp_reg(par, CARMINE_DISP_REG_L3_DISP_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) c_set_disp_reg(par, CARMINE_DISP_REG_L4_DISP_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) c_set_disp_reg(par, CARMINE_DISP_REG_L5_DISP_ADR1, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) c_set_disp_reg(par, CARMINE_DISP_REG_L6_DISP_ADR0, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) c_set_disp_reg(par, CARMINE_DISP_REG_L7_DISP_ADR0, soffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Set default display position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) c_set_disp_reg(par, CARMINE_DISP_REG_L0_DISP_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) c_set_disp_reg(par, CARMINE_DISP_REG_L2_DISP_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) c_set_disp_reg(par, CARMINE_DISP_REG_L3_DISP_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) c_set_disp_reg(par, CARMINE_DISP_REG_L4_DISP_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) c_set_disp_reg(par, CARMINE_DISP_REG_L5_DISP_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) c_set_disp_reg(par, CARMINE_DISP_REG_L6_DISP_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) c_set_disp_reg(par, CARMINE_DISP_REG_L7_DISP_POS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Set default blend mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* default transparency mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) c_set_disp_reg(par, CARMINE_DISP_REG_L0_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) c_set_disp_reg(par, CARMINE_DISP_REG_L1_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) c_set_disp_reg(par, CARMINE_DISP_REG_L2_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) c_set_disp_reg(par, CARMINE_DISP_REG_L3_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) c_set_disp_reg(par, CARMINE_DISP_REG_L4_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) c_set_disp_reg(par, CARMINE_DISP_REG_L5_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) c_set_disp_reg(par, CARMINE_DISP_REG_L6_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) c_set_disp_reg(par, CARMINE_DISP_REG_L7_TRANS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Set default read skip parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) c_set_disp_reg(par, CARMINE_DISP_REG_L0RM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) c_set_disp_reg(par, CARMINE_DISP_REG_L2RM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) c_set_disp_reg(par, CARMINE_DISP_REG_L3RM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) c_set_disp_reg(par, CARMINE_DISP_REG_L4RM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) c_set_disp_reg(par, CARMINE_DISP_REG_L5RM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) c_set_disp_reg(par, CARMINE_DISP_REG_L6RM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) c_set_disp_reg(par, CARMINE_DISP_REG_L7RM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) c_set_disp_reg(par, CARMINE_DISP_REG_L0PX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) c_set_disp_reg(par, CARMINE_DISP_REG_L2PX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) c_set_disp_reg(par, CARMINE_DISP_REG_L3PX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) c_set_disp_reg(par, CARMINE_DISP_REG_L4PX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) c_set_disp_reg(par, CARMINE_DISP_REG_L5PX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) c_set_disp_reg(par, CARMINE_DISP_REG_L6PX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) c_set_disp_reg(par, CARMINE_DISP_REG_L7PX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) c_set_disp_reg(par, CARMINE_DISP_REG_L0PY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) c_set_disp_reg(par, CARMINE_DISP_REG_L2PY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) c_set_disp_reg(par, CARMINE_DISP_REG_L3PY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) c_set_disp_reg(par, CARMINE_DISP_REG_L4PY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) c_set_disp_reg(par, CARMINE_DISP_REG_L5PY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) c_set_disp_reg(par, CARMINE_DISP_REG_L6PY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) c_set_disp_reg(par, CARMINE_DISP_REG_L7PY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void set_display_parameters(struct carmine_fb *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * display timing. Parameters are decreased by one because hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * spec is 0 to (n - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) hdp = par->res->hdp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) vdp = par->res->vdp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) htp = par->res->htp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) hsp = par->res->hsp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) hsw = par->res->hsw - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) vtr = par->res->vtr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) vsp = par->res->vsp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) vsw = par->res->vsw - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) c_set_disp_reg(par, CARMINE_DISP_REG_H_TOTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) htp << CARMINE_DISP_HTP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) c_set_disp_reg(par, CARMINE_DISP_REG_H_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (hdp << CARMINE_DISP_HDB_SHIFT) | hdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) c_set_disp_reg(par, CARMINE_DISP_REG_V_H_W_H_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) (vsw << CARMINE_DISP_VSW_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) (hsw << CARMINE_DISP_HSW_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (hsp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) c_set_disp_reg(par, CARMINE_DISP_REG_V_TOTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) vtr << CARMINE_DISP_VTR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) c_set_disp_reg(par, CARMINE_DISP_REG_V_PERIOD_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) (vdp << CARMINE_DISP_VDP_SHIFT) | vsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mode = c_get_disp_reg(par, CARMINE_DISP_REG_DCM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mode = (mode & ~CARMINE_DISP_DCM_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) (par->res->disp_mode & CARMINE_DISP_DCM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* enable video output and layer 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mode |= CARMINE_DEN | CARMINE_L0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) c_set_disp_reg(par, CARMINE_DISP_REG_DCM1, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int carmine_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct carmine_fb *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = carmine_find_mode(&info->var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) par->new_mode = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (par->cur_mode != par->new_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) par->cur_mode = par->new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) par->res = &car_modes[par->new_mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) carmine_init_display_param(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) set_display_parameters(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) info->fix.line_length = info->var.xres * info->var.bits_per_pixel / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int init_hardware(struct carmine_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Initialize Carmine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Sets internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CARMINE_DFLT_IP_CLOCK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Video signal output is turned off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) c_set_hw_reg(hw, CARMINE_DISP0_REG + CARMINE_DISP_REG_DCM1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) c_set_hw_reg(hw, CARMINE_DISP1_REG + CARMINE_DISP_REG_DCM1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_SOFTWARE_RESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_SOFTWARE_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* I/O mode settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) flags = CARMINE_DFLT_IP_DCTL_IO_CONT1 << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) CARMINE_DFLT_IP_DCTL_IO_CONT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_IOCONT1_IOCONT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* DRAM initial sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) flags = CARMINE_DFLT_IP_DCTL_MODE << 16 | CARMINE_DFLT_IP_DCTL_ADD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_MODE_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) flags = CARMINE_DFLT_IP_DCTL_SET_TIME1 << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) CARMINE_DFLT_IP_DCTL_EMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_SETTIME1_EMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) flags = CARMINE_DFLT_IP_DCTL_REFRESH << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) CARMINE_DFLT_IP_DCTL_SET_TIME2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_REFRESH_SETTIME2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) flags = CARMINE_DFLT_IP_DCTL_RESERVE2 << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CARMINE_DFLT_IP_DCTL_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV2_RSV1, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) flags = CARMINE_DFLT_IP_DCTL_DDRIF2 << 16 | CARMINE_DFLT_IP_DCTL_DDRIF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_DDRIF2_DDRIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) flags = CARMINE_DFLT_IP_DCTL_RESERVE0 << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CARMINE_DFLT_IP_DCTL_STATES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV0_STATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Executes DLL reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (CARMINE_DCTL_DLL_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for (loops = 0; loops < CARMINE_DCTL_INIT_WAIT_LIMIT; loops++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = c_get_hw_reg(hw, CARMINE_DCTL_REG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) CARMINE_DCTL_REG_RSV0_STATES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret &= CARMINE_DCTL_REG_STATES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mdelay(CARMINE_DCTL_INIT_WAIT_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (loops >= CARMINE_DCTL_INIT_WAIT_LIMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) printk(KERN_ERR "DRAM init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) flags = CARMINE_DFLT_IP_DCTL_MODE_AFT_RST << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) CARMINE_DFLT_IP_DCTL_ADD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_MODE_ADD, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) flags = CARMINE_DFLT_IP_DCTL_RESERVE0 << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) CARMINE_DFLT_IP_DCTL_STATES_AFT_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV0_STATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Initialize the write back register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) c_set_hw_reg(hw, CARMINE_WB_REG + CARMINE_WB_REG_WBM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) CARMINE_WB_REG_WBM_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Initialize the Kottos registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_VRINTM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_VRERRM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Set DC offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_PX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_PY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_LX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_LY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_TX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_TY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct fb_ops carminefb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .fb_check_var = carmine_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .fb_set_par = carmine_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .fb_setcolreg = carmine_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int alloc_carmine_fb(void __iomem *regs, void __iomem *smem_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int smem_offset, struct device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct fb_info **rinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct carmine_fb *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) info = framebuffer_alloc(sizeof *par, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) par->display_reg = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) par->smem_offset = smem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) info->screen_base = smem_base + smem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) info->screen_size = CARMINE_DISPLAY_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) info->fbops = &carminefb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) info->fix = carminefb_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) info->pseudo_palette = par->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) info->flags = FBINFO_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = fb_alloc_cmap(&info->cmap, 256, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto err_free_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (fb_mode >= ARRAY_SIZE(carmine_modedb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fb_mode = CARMINEFB_DEFAULT_VIDEO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) par->cur_mode = par->new_mode = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = fb_find_mode(&info->var, info, fb_mode_str, carmine_modedb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ARRAY_SIZE(carmine_modedb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) &carmine_modedb[fb_mode], 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (!ret || ret == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) goto err_dealloc_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) fb_videomode_to_modelist(carmine_modedb, ARRAY_SIZE(carmine_modedb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = register_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) goto err_dealloc_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) fb_info(info, "%s frame buffer device\n", info->fix.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *rinfo = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) err_dealloc_cmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) err_free_fb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void cleanup_fb_device(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int carminefb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct carmine_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct device *device = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) hw = kzalloc(sizeof *hw, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto err_enable_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) carminefb_fix.mmio_start = pci_resource_start(dev, CARMINE_CONFIG_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) carminefb_fix.mmio_len = pci_resource_len(dev, CARMINE_CONFIG_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!request_mem_region(carminefb_fix.mmio_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) carminefb_fix.mmio_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "carminefb regbase")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) printk(KERN_ERR "carminefb: Can't reserve regbase.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto err_free_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) hw->v_regs = ioremap(carminefb_fix.mmio_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) carminefb_fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (!hw->v_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) printk(KERN_ERR "carminefb: Can't remap %s register.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) carminefb_fix.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) goto err_free_reg_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) carminefb_fix.smem_start = pci_resource_start(dev, CARMINE_MEMORY_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) carminefb_fix.smem_len = pci_resource_len(dev, CARMINE_MEMORY_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* The memory area tends to be very large (256 MiB). Remap only what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * is required for that largest resolution to avoid remaps at run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (carminefb_fix.smem_len > CARMINE_TOTAL_DIPLAY_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) carminefb_fix.smem_len = CARMINE_TOTAL_DIPLAY_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) else if (carminefb_fix.smem_len < CARMINE_TOTAL_DIPLAY_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) printk(KERN_ERR "carminefb: Memory bar is only %d bytes, %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "are required.", carminefb_fix.smem_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) CARMINE_TOTAL_DIPLAY_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto err_unmap_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!request_mem_region(carminefb_fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) carminefb_fix.smem_len, "carminefb smem")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) printk(KERN_ERR "carminefb: Can't reserve smem.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) goto err_unmap_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) hw->screen_mem = ioremap(carminefb_fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) carminefb_fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (!hw->screen_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) printk(KERN_ERR "carmine: Can't ioremap smem area.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) goto err_reg_smem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = init_hardware(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) goto err_unmap_screen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (fb_displays & CARMINE_USE_DISPLAY0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = alloc_carmine_fb(hw->v_regs + CARMINE_DISP0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) hw->screen_mem, CARMINE_DISPLAY_MEM * 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) device, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) goto err_deinit_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) hw->fb[0] = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (fb_displays & CARMINE_USE_DISPLAY1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = alloc_carmine_fb(hw->v_regs + CARMINE_DISP1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) hw->screen_mem, CARMINE_DISPLAY_MEM * 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) device, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) goto err_cleanup_fb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) hw->fb[1] = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pci_set_drvdata(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) err_cleanup_fb0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) cleanup_fb_device(hw->fb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) err_deinit_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* disable clock, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) err_unmap_screen:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) iounmap(hw->screen_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) err_reg_smem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) release_mem_region(carminefb_fix.smem_start, carminefb_fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) err_unmap_vregs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) iounmap(hw->v_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) err_free_reg_mmio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) release_mem_region(carminefb_fix.mmio_start, carminefb_fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) err_free_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) kfree(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) err_enable_pci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static void carminefb_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct carmine_hw *hw = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct fb_fix_screeninfo fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* in case we use only fb1 and not fb1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (hw->fb[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) fix = hw->fb[0]->fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) fix = hw->fb[1]->fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* deactivate display(s) and switch clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) c_set_hw_reg(hw, CARMINE_DISP0_REG + CARMINE_DISP_REG_DCM1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) c_set_hw_reg(hw, CARMINE_DISP1_REG + CARMINE_DISP_REG_DCM1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) for (i = 0; i < MAX_DISPLAY; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) cleanup_fb_device(hw->fb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) iounmap(hw->screen_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) release_mem_region(fix.smem_start, fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) iounmap(hw->v_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) release_mem_region(fix.mmio_start, fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) kfree(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define PCI_VENDOR_ID_FUJITU_LIMITED 0x10cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct pci_device_id carmine_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PCI_DEVICE(PCI_VENDOR_ID_FUJITU_LIMITED, 0x202b)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0, 0, 0, 0, 0, 0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MODULE_DEVICE_TABLE(pci, carmine_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static struct pci_driver carmine_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .name = "carminefb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .id_table = carmine_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .probe = carminefb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .remove = carminefb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int __init carminefb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!(fb_displays &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) (CARMINE_USE_DISPLAY0 | CARMINE_USE_DISPLAY1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) printk(KERN_ERR "If you disable both displays than you don't "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "need the driver at all\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return pci_register_driver(&carmine_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) module_init(carminefb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static void __exit carminefb_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pci_unregister_driver(&carmine_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) module_exit(carminefb_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) MODULE_AUTHOR("Sebastian Siewior <bigeasy@linutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) MODULE_DESCRIPTION("Framebuffer driver for Fujitsu Carmine based devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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