Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *	linux/drivers/video/bt455.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	Copyright 2003  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	Copyright 2016  Maciej W. Rozycki <macro@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	Public License. See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *	archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Bt455 byte-wide registers, 32-bit aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct bt455_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	volatile u8 addr_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	u8 pad0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	volatile u8 addr_cmap_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	u8 pad1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	volatile u8 addr_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	u8 pad2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	volatile u8 addr_ovly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u8 pad3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static inline void bt455_select_reg(struct bt455_regs *regs, int ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	regs->addr_cmap = ir & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline void bt455_reset_reg(struct bt455_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	regs->addr_clr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * Read/write to a Bt455 color map register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline void bt455_read_cmap_next(struct bt455_regs *regs, u8 *grey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	regs->addr_cmap_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	*grey = regs->addr_cmap_data & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	regs->addr_cmap_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline void bt455_write_cmap_next(struct bt455_regs *regs, u8 grey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	regs->addr_cmap_data = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	regs->addr_cmap_data = grey & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	regs->addr_cmap_data = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline void bt455_write_ovly_next(struct bt455_regs *regs, u8 grey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	regs->addr_ovly = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	regs->addr_ovly = grey & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	regs->addr_ovly = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline void bt455_read_cmap_entry(struct bt455_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 					 int cr, u8 *grey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	bt455_select_reg(regs, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	bt455_read_cmap_next(regs, grey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void bt455_write_cmap_entry(struct bt455_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 					  int cr, u8 grey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	bt455_select_reg(regs, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	bt455_write_cmap_next(regs, grey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline void bt455_write_ovly_entry(struct bt455_regs *regs, u8 grey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	bt455_reset_reg(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	bt455_write_ovly_next(regs, grey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }