Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *	linux/drivers/video/bt431.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *	Copyright 2003  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	Copyright 2016  Maciej W. Rozycki <macro@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Public License. See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *	archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define BT431_CURSOR_SIZE	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Bt431 cursor generator registers, 32-bit aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Two twin Bt431 are used on the DECstation's PMAG-AA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct bt431_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	volatile u16 addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u16 pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	volatile u16 addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u16 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	volatile u16 addr_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u16 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	volatile u16 addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u16 pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static inline u16 bt431_set_value(u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	return ((val << 8) | (val & 0xff)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static inline u8 bt431_get_value(u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	return val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * Additional registers addressed indirectly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BT431_REG_CMD		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BT431_REG_CXLO		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define BT431_REG_CXHI		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define BT431_REG_CYLO		0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define BT431_REG_CYHI		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BT431_REG_WXLO		0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BT431_REG_WXHI		0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BT431_REG_WYLO		0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BT431_REG_WYHI		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define BT431_REG_WWLO		0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BT431_REG_WWHI		0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BT431_REG_WHLO		0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define BT431_REG_WHHI		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BT431_REG_CRAM_BASE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BT431_REG_CRAM_END	0x01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * Command register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define BT431_CMD_CURS_ENABLE	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define BT431_CMD_XHAIR_ENABLE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define BT431_CMD_OR_CURSORS	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define BT431_CMD_XOR_CURSORS	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define BT431_CMD_1_1_MUX	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define BT431_CMD_4_1_MUX	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define BT431_CMD_5_1_MUX	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define BT431_CMD_xxx_MUX	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define BT431_CMD_THICK_1	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define BT431_CMD_THICK_3	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define BT431_CMD_THICK_5	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define BT431_CMD_THICK_7	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static inline void bt431_select_reg(struct bt431_regs *regs, int ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * The compiler splits the write in two bytes without these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * helper variables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	volatile u16 *lo = &(regs->addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	volatile u16 *hi = &(regs->addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	*lo = bt431_set_value(ir & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	*hi = bt431_set_value((ir >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* Autoincrement read/write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static inline u8 bt431_read_reg_inc(struct bt431_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * The compiler splits the write in two bytes without the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * helper variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	volatile u16 *r = &(regs->addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return bt431_get_value(*r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void bt431_write_reg_inc(struct bt431_regs *regs, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * The compiler splits the write in two bytes without the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * helper variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	volatile u16 *r = &(regs->addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	*r = bt431_set_value(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline u8 bt431_read_reg(struct bt431_regs *regs, int ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	bt431_select_reg(regs, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return bt431_read_reg_inc(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline void bt431_write_reg(struct bt431_regs *regs, int ir, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	bt431_select_reg(regs, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	bt431_write_reg_inc(regs, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Autoincremented read/write for the cursor map. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline u16 bt431_read_cmap_inc(struct bt431_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 * The compiler splits the write in two bytes without the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * helper variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	volatile u16 *r = &(regs->addr_cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline void bt431_write_cmap_inc(struct bt431_regs *regs, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 * The compiler splits the write in two bytes without the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 * helper variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	volatile u16 *r = &(regs->addr_cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	*r = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline u16 bt431_read_cmap(struct bt431_regs *regs, int cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	bt431_select_reg(regs, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return bt431_read_cmap_inc(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline void bt431_write_cmap(struct bt431_regs *regs, int cr, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	bt431_select_reg(regs, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	bt431_write_cmap_inc(regs, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline void bt431_enable_cursor(struct bt431_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	bt431_write_reg(regs, BT431_REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			BT431_CMD_CURS_ENABLE | BT431_CMD_OR_CURSORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			| BT431_CMD_4_1_MUX | BT431_CMD_THICK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void bt431_erase_cursor(struct bt431_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	bt431_write_reg(regs, BT431_REG_CMD, BT431_CMD_4_1_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline void bt431_position_cursor(struct bt431_regs *regs, u16 x, u16 y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * Magic from the MACH sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 * Cx = x + D + H - P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 *  P = 37 if 1:1, 52 if 4:1, 57 if 5:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 *  D = pixel skew between outdata and external data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 *  H = pixels between HSYNCH falling and active video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * Cy = y + V - 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 *  V = scanlines between HSYNCH falling, two or more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 *      clocks after VSYNCH falling, and active video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	x += 412 - 52;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	y += 68 - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* Use autoincrement. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	bt431_select_reg(regs, BT431_REG_CXLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	bt431_write_reg_inc(regs, x & 0xff); /* BT431_REG_CXLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	bt431_write_reg_inc(regs, (x >> 8) & 0x0f); /* BT431_REG_CXHI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	bt431_write_reg_inc(regs, y & 0xff); /* BT431_REG_CYLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bt431_write_reg_inc(regs, (y >> 8) & 0x0f); /* BT431_REG_CYHI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline void bt431_set_cursor(struct bt431_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				    const char *data, const char *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				    u16 rop, u16 width, u16 height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u16 x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	width = DIV_ROUND_UP(width, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	bt431_select_reg(regs, BT431_REG_CRAM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	for (y = 0; y < BT431_CURSOR_SIZE; y++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		for (x = 0; x < BT431_CURSOR_SIZE / 8; x++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			u16 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			if (y < height && x < width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				val = mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				if (rop == ROP_XOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 					val = (val << 8) | (val ^ data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					val = (val << 8) | (val & data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			bt431_write_cmap_inc(regs, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline void bt431_init_cursor(struct bt431_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* no crosshair window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	bt431_select_reg(regs, BT431_REG_WXLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	bt431_write_reg_inc(regs, 0x00); /* BT431_REG_WXLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	bt431_write_reg_inc(regs, 0x00); /* BT431_REG_WXHI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	bt431_write_reg_inc(regs, 0x00); /* BT431_REG_WYLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	bt431_write_reg_inc(regs, 0x00); /* BT431_REG_WYHI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	bt431_write_reg_inc(regs, 0x00); /* BT431_REG_WWLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	bt431_write_reg_inc(regs, 0x00); /* BT431_REG_WWHI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	bt431_write_reg_inc(regs, 0x00); /* BT431_REG_WHLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	bt431_write_reg_inc(regs, 0x00); /* BT431_REG_WHHI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }