Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * BRIEF MODULE DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *	Hardware definitions for the Au1200 LCD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2004 AMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:	AMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  This program is free software; you can redistribute	 it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  under  the terms of	 the GNU General  Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Free Software Foundation;  either version 2 of the	License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *  with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifndef _AU1200LCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define _AU1200LCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AU1200_LCD_ADDR		0xB5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define uint8 unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define uint32 unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct au1200_lcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	volatile uint32	reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	volatile uint32	screen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	volatile uint32	backcolor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	volatile uint32	horztiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	volatile uint32	verttiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	volatile uint32	clkcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	volatile uint32	pwmdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	volatile uint32	pwmhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	volatile uint32	reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	volatile uint32	winenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	volatile uint32	colorkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	volatile uint32	colorkeymsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		volatile uint32	cursorctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		volatile uint32	cursorpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		volatile uint32	cursorcolor0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		volatile uint32	cursorcolor1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		volatile uint32	cursorcolor2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		uint32	cursorcolor3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	} hwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	volatile uint32	intstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	volatile uint32	intenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	volatile uint32	outmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	volatile uint32	fifoctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	uint32	reserved2[(0x0100-0x0058)/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		volatile uint32	winctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		volatile uint32	winctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		volatile uint32	winctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		volatile uint32	winbuf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		volatile uint32	winbuf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		volatile uint32	winbufctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		uint32	winreserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		uint32	winreserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	} window[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	uint32	reserved3[(0x0400-0x0180)/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	volatile uint32	palette[(0x0800-0x0400)/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	volatile uint8	cursorpattern[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* lcd_screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define LCD_SCREEN_SEN		(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define LCD_SCREEN_SX		(0x07FF<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define LCD_SCREEN_SY		(0x07FF<< 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define LCD_SCREEN_SWP		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define LCD_SCREEN_SWD		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define LCD_SCREEN_PT		(7<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define LCD_SCREEN_PT_TFT	(0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define LCD_SCREEN_SX_N(WIDTH)	((WIDTH-1)<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define LCD_SCREEN_SY_N(HEIGHT)	((HEIGHT-1)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define LCD_SCREEN_PT_CSTN	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define LCD_SCREEN_PT_CDSTN	(2<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define LCD_SCREEN_PT_M8STN	(3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define LCD_SCREEN_PT_M4STN	(4<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* lcd_backcolor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LCD_BACKCOLOR_SBGR		(0xFF<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LCD_BACKCOLOR_SBGG		(0xFF<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LCD_BACKCOLOR_SBGB		(0xFF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LCD_BACKCOLOR_SBGR_N(N)	((N)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LCD_BACKCOLOR_SBGG_N(N)	((N)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LCD_BACKCOLOR_SBGB_N(N)	((N)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* lcd_winenable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LCD_WINENABLE_WEN3		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LCD_WINENABLE_WEN2		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LCD_WINENABLE_WEN1		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LCD_WINENABLE_WEN0		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* lcd_colorkey */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LCD_COLORKEY_CKR		(0xFF<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LCD_COLORKEY_CKG		(0xFF<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LCD_COLORKEY_CKB		(0xFF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LCD_COLORKEY_CKR_N(N)	((N)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LCD_COLORKEY_CKG_N(N)	((N)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LCD_COLORKEY_CKB_N(N)	((N)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* lcd_colorkeymsk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LCD_COLORKEYMSK_CKMR		(0xFF<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LCD_COLORKEYMSK_CKMG		(0xFF<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LCD_COLORKEYMSK_CKMB		(0xFF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LCD_COLORKEYMSK_CKMR_N(N)	((N)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LCD_COLORKEYMSK_CKMG_N(N)	((N)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LCD_COLORKEYMSK_CKMB_N(N)	((N)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* lcd windows control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LCD_WINCTRL0_OX		(0x07FF<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LCD_WINCTRL0_OY		(0x07FF<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LCD_WINCTRL0_A		(0x00FF<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LCD_WINCTRL0_AEN	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LCD_WINCTRL0_OX_N(N) ((N)<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LCD_WINCTRL0_OY_N(N) ((N)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LCD_WINCTRL0_A_N(N) ((N)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* lcd windows control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LCD_WINCTRL1_PRI	(3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LCD_WINCTRL1_PIPE	(1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LCD_WINCTRL1_FRM	(0xF<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LCD_WINCTRL1_CCO	(1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LCD_WINCTRL1_PO		(3<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LCD_WINCTRL1_SZX	(0x07FF<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LCD_WINCTRL1_SZY	(0x07FF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LCD_WINCTRL1_FRM_1BPP	(0<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LCD_WINCTRL1_FRM_2BPP	(1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LCD_WINCTRL1_FRM_4BPP	(2<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LCD_WINCTRL1_FRM_8BPP	(3<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LCD_WINCTRL1_FRM_12BPP	(4<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LCD_WINCTRL1_FRM_16BPP655	(5<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LCD_WINCTRL1_FRM_16BPP565	(6<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LCD_WINCTRL1_FRM_16BPP556	(7<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LCD_WINCTRL1_FRM_16BPPI1555	(8<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LCD_WINCTRL1_FRM_16BPPI5551	(9<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LCD_WINCTRL1_FRM_16BPPA1555	(10<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LCD_WINCTRL1_FRM_16BPPA5551	(11<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LCD_WINCTRL1_FRM_24BPP		(12<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LCD_WINCTRL1_FRM_32BPP		(13<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LCD_WINCTRL1_PRI_N(N)	((N)<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LCD_WINCTRL1_PO_00		(0<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define LCD_WINCTRL1_PO_01		(1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LCD_WINCTRL1_PO_10		(2<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LCD_WINCTRL1_PO_11		(3<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LCD_WINCTRL1_SZX_N(N)	((N-1)<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LCD_WINCTRL1_SZY_N(N)	((N-1)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* lcd windows control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LCD_WINCTRL2_CKMODE		(3<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LCD_WINCTRL2_DBM		(1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define LCD_WINCTRL2_RAM		(3<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define LCD_WINCTRL2_BX			(0x1FFF<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define LCD_WINCTRL2_SCX		(0xF<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define LCD_WINCTRL2_SCY		(0xF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define LCD_WINCTRL2_CKMODE_00		(0<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define LCD_WINCTRL2_CKMODE_01		(1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define LCD_WINCTRL2_CKMODE_10		(2<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LCD_WINCTRL2_CKMODE_11		(3<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define LCD_WINCTRL2_RAM_NONE		(0<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define LCD_WINCTRL2_RAM_PALETTE	(1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define LCD_WINCTRL2_RAM_GAMMA		(2<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define LCD_WINCTRL2_RAM_BUFFER		(3<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define LCD_WINCTRL2_BX_N(N)	((N)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define LCD_WINCTRL2_SCX_1		(0<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define LCD_WINCTRL2_SCX_2		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define LCD_WINCTRL2_SCX_4		(2<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define LCD_WINCTRL2_SCY_1		(0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LCD_WINCTRL2_SCY_2		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LCD_WINCTRL2_SCY_4		(2<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* lcd windows buffer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LCD_WINBUFCTRL_DB		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LCD_WINBUFCTRL_DBN		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* lcd_intstatus, lcd_intenable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LCD_INT_IFO				(0xF<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define LCD_INT_IFU				(0xF<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LCD_INT_OFO				(1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LCD_INT_OFU				(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define LCD_INT_WAIT			(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LCD_INT_SD				(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LCD_INT_SA				(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LCD_INT_SS				(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* lcd_horztiming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LCD_HORZTIMING_HND2		(0x1FF<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define LCD_HORZTIMING_HND1		(0x1FF<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LCD_HORZTIMING_HPW		(0x1FF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define LCD_HORZTIMING_HND2_N(N)(((N)-1)<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define LCD_HORZTIMING_HND1_N(N)(((N)-1)<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define LCD_HORZTIMING_HPW_N(N)	(((N)-1)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* lcd_verttiming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define LCD_VERTTIMING_VND2		(0x1FF<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define LCD_VERTTIMING_VND1		(0x1FF<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LCD_VERTTIMING_VPW		(0x1FF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define LCD_VERTTIMING_VND2_N(N)(((N)-1)<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define LCD_VERTTIMING_VND1_N(N)(((N)-1)<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define LCD_VERTTIMING_VPW_N(N)	(((N)-1)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* lcd_clkcontrol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define LCD_CLKCONTROL_EXT		(1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define LCD_CLKCONTROL_DELAY	(3<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define LCD_CLKCONTROL_CDD		(1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define LCD_CLKCONTROL_IB		(1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define LCD_CLKCONTROL_IC		(1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define LCD_CLKCONTROL_IH		(1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define LCD_CLKCONTROL_IV		(1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define LCD_CLKCONTROL_BF		(0x1F<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define LCD_CLKCONTROL_PCD		(0x3FF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define LCD_CLKCONTROL_BF_N(N)	(((N)-1)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define LCD_CLKCONTROL_PCD_N(N)	((N)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* lcd_pwmdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define LCD_PWMDIV_EN			(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define LCD_PWMDIV_PWMDIV		(0x1FFFF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define LCD_PWMDIV_PWMDIV_N(N)	((N)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* lcd_pwmhi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define LCD_PWMHI_PWMHI1		(0xFFFF<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define LCD_PWMHI_PWMHI0		(0xFFFF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define LCD_PWMHI_PWMHI1_N(N)	((N)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define LCD_PWMHI_PWMHI0_N(N)	((N)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* lcd_hwccon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define LCD_HWCCON_EN			(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* lcd_cursorpos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define LCD_CURSORPOS_HWCXOFF		(0x1F<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define LCD_CURSORPOS_HWCXPOS		(0x07FF<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define LCD_CURSORPOS_HWCYOFF		(0x1F<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define LCD_CURSORPOS_HWCYPOS		(0x07FF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define LCD_CURSORPOS_HWCXOFF_N(N)	((N)<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define LCD_CURSORPOS_HWCXPOS_N(N)	((N)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define LCD_CURSORPOS_HWCYOFF_N(N)	((N)<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define LCD_CURSORPOS_HWCYPOS_N(N)	((N)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* lcd_cursorcolor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define LCD_CURSORCOLOR_HWCA		(0xFF<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define LCD_CURSORCOLOR_HWCR		(0xFF<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define LCD_CURSORCOLOR_HWCG		(0xFF<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define LCD_CURSORCOLOR_HWCB		(0xFF<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define LCD_CURSORCOLOR_HWCA_N(N)	((N)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define LCD_CURSORCOLOR_HWCR_N(N)	((N)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define LCD_CURSORCOLOR_HWCG_N(N)	((N)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define LCD_CURSORCOLOR_HWCB_N(N)	((N)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* lcd_fifoctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define LCD_FIFOCTRL_F3IF		(1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define LCD_FIFOCTRL_F3REQ		(0x1F<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define LCD_FIFOCTRL_F2IF		(1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define LCD_FIFOCTRL_F2REQ		(0x1F<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define LCD_FIFOCTRL_F1IF		(1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define LCD_FIFOCTRL_F1REQ		(0x1F<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define LCD_FIFOCTRL_F0IF		(1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define LCD_FIFOCTRL_F0REQ		(0x1F<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define LCD_FIFOCTRL_F3REQ_N(N)	((N-1)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define LCD_FIFOCTRL_F2REQ_N(N)	((N-1)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define LCD_FIFOCTRL_F1REQ_N(N)	((N-1)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define LCD_FIFOCTRL_F0REQ_N(N)	((N-1)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* lcd_outmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LCD_OUTMASK_MASK		(0x00FFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif /* _AU1200LCD_H */