^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * BRIEF MODULE DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hardware definitions for the Au1100 LCD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2002 MontaVista Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2002 Alchemy Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Alchemy Semiconductor, MontaVista Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef _AU1100LCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define _AU1100LCD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #if DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define print_dbg(f, arg...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #if defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* LCD controller restrictions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AU1100_LCD_MAX_XRES 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AU1100_LCD_MAX_YRES 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AU1100_LCD_MAX_BPP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AU1100_LCD_MAX_CLK 48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AU1100_LCD_NBR_PALETTE_ENTRIES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Default number of visible screen buffer to allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AU1100FB_NBR_VIDEO_BUFFERS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct au1100fb_panel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const char name[25]; /* Full name <vendor>_<model> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 control_base; /* Mode-independent control values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 clkcontrol_base; /* Panel pixclock preferences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 horztiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 verttiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 xres; /* Maximum horizontal resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 yres; /* Maximum vertical resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 bpp; /* Maximum depth supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct au1100fb_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 lcd_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 lcd_intstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 lcd_intenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 lcd_horztiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 lcd_verttiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 lcd_clkcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 lcd_dmaaddr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 lcd_dmaaddr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 lcd_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 lcd_pwmdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 lcd_pwmhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 reserved[(0x0400-0x002C)/4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 lcd_pallettebase[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct au1100fb_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct fb_info info; /* FB driver info record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct au1100fb_panel *panel; /* Panel connected to this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct au1100fb_regs* regs; /* Registers memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) size_t regs_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int regs_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned char* fb_mem; /* FrameBuffer memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) size_t fb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dma_addr_t fb_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int panel_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct clk *lcdclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LCD_CONTROL_SBB_BIT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LCD_CONTROL_SBPPF_BIT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LCD_CONTROL_WP (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LCD_CONTROL_WD (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LCD_CONTROL_C (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LCD_CONTROL_SM_BIT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LCD_CONTROL_DB (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LCD_CONTROL_CCO (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LCD_CONTROL_DP (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LCD_CONTROL_PO_BIT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LCD_CONTROL_MPI (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LCD_CONTROL_PT (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LCD_CONTROL_PC (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LCD_CONTROL_BPP_BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LCD_CONTROL_GO (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LCD_INT_SD (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LCD_INT_OF (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LCD_INT_UF (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LCD_INT_SA (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LCD_INT_SS (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LCD_INT_S1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define LCD_INT_S0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define LCD_HORZTIMING_HN2_BIT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define LCD_HORZTIMING_HN1_BIT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define LCD_HORZTIMING_HPW_BIT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define LCD_HORZTIMING_PPL_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LCD_VERTTIMING_VN2_BIT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define LCD_VERTTIMING_VN1_BIT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define LCD_VERTTIMING_VPW_BIT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define LCD_VERTTIMING_LPP_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LCD_CLKCONTROL_IB (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LCD_CLKCONTROL_IC (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define LCD_CLKCONTROL_IH (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define LCD_CLKCONTROL_IV (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LCD_CLKCONTROL_BF_BIT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define LCD_CLKCONTROL_PCD_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define LCD_DMA_SA_BIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define LCD_WORDS (AU1100_LCD_BASE + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define LCD_WRD_WRDS_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define LCD_PWMDIV_EN (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define LCD_PWMDIV_PWMDIV_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define LCD_PWMHI_PWMHI1_BIT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define LCD_PWMHI_PWMHI0_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define LCD_PALLETTE_MONO_MI_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define LCD_PALLETTE_COLOR_RI_BIT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define LCD_PALLETTE_COLOR_GI_BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define LCD_PALLETTE_COLOR_BI_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define LCD_PALLETTE_TFT_DC_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* List of panels known to work with the AU1100 LCD controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * To add a new panel, enter the same specifications as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Generic_TFT one, and MAKE SURE that it doesn't conflicts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * with the controller restrictions. Restrictions are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * STN color panels: max_bpp <= 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * STN mono panels: max_bpp <= 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * TFT panels: max_bpp <= 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * max_xres <= 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * max_yres <= 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct au1100fb_panel known_lcd_panels[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* 800x600x16bpp CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .name = "CRT_800x600_16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .yres = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .control_base = 0x0004886A |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .clkcontrol_base = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .horztiming = 0x005aff1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .verttiming = 0x16000e57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* just the standard LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .name = "WWPC LCD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .xres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .yres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .control_base = 0x0006806A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .horztiming = 0x0A1010EF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .verttiming = 0x0301013F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .clkcontrol_base = 0x00018001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Sharp 320x240 TFT panel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "Sharp_LQ038Q5DR01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .xres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .yres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .control_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ( LCD_CONTROL_SBPPF_565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) | LCD_CONTROL_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) | LCD_CONTROL_SM_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) | LCD_CONTROL_DEFAULT_PO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) | LCD_CONTROL_PT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) | LCD_CONTROL_PC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) | LCD_CONTROL_BPP_16 ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .horztiming =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ( LCD_HORZTIMING_HN2_N(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) | LCD_HORZTIMING_HN1_N(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) | LCD_HORZTIMING_HPW_N(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) | LCD_HORZTIMING_PPL_N(320) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .verttiming =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ( LCD_VERTTIMING_VN2_N(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) | LCD_VERTTIMING_VN1_N(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) | LCD_VERTTIMING_VPW_N(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) | LCD_VERTTIMING_LPP_N(240) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Hitachi SP14Q005 and possibly others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .name = "Hitachi_SP14Qxxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .xres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .yres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .bpp = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .control_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ( LCD_CONTROL_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) | LCD_CONTROL_BPP_4 ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .horztiming =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ( LCD_HORZTIMING_HN2_N(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) | LCD_HORZTIMING_HN1_N(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) | LCD_HORZTIMING_HPW_N(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) | LCD_HORZTIMING_PPL_N(320) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .verttiming =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ( LCD_VERTTIMING_VN2_N(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) | LCD_VERTTIMING_VN1_N(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) | LCD_VERTTIMING_VPW_N(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) | LCD_VERTTIMING_LPP_N(240) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Generic 640x480 TFT panel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "TFT_640x480_16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .horztiming = 0x3434d67f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .verttiming = 0x0e0e39df,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Pb1100 LCDB 640x480 PrimeView TFT panel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .name = "PrimeView_640x480_16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .horztiming = 0x0e4bfe7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .verttiming = 0x210805df,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .clkcontrol_base = 0x00038001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Inline helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif /* _AU1100LCD_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags