^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __RADEONFB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __RADEONFB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifdef CONFIG_FB_RADEON_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifdef CONFIG_FB_RADEON_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <video/radeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /***************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Most of the definitions here are adapted right from XFree86 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ***************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Chip families. Must fit in the low 16 bits of a long word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum radeon_family {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CHIP_FAMILY_UNKNOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CHIP_FAMILY_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CHIP_FAMILY_RADEON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CHIP_FAMILY_RV100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CHIP_FAMILY_RV200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RS250 (IGP 7000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CHIP_FAMILY_R200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CHIP_FAMILY_RV250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) CHIP_FAMILY_RV280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) CHIP_FAMILY_R300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CHIP_FAMILY_R350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CHIP_FAMILY_RV350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CHIP_FAMILY_R420, /* R420/R423/M18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CHIP_FAMILY_RC410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CHIP_FAMILY_RS400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CHIP_FAMILY_RS480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CHIP_FAMILY_LAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ((rinfo)->family == CHIP_FAMILY_RV200) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ((rinfo)->family == CHIP_FAMILY_RS100) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ((rinfo)->family == CHIP_FAMILY_RS200) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ((rinfo)->family == CHIP_FAMILY_RV250) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ((rinfo)->family == CHIP_FAMILY_RV280) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ((rinfo)->family == CHIP_FAMILY_RS300))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ((rinfo)->family == CHIP_FAMILY_RV350) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ((rinfo)->family == CHIP_FAMILY_R350) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ((rinfo)->family == CHIP_FAMILY_RV380) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ((rinfo)->family == CHIP_FAMILY_R420) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((rinfo)->family == CHIP_FAMILY_RC410) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ((rinfo)->family == CHIP_FAMILY_RS480))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Chip flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum radeon_chip_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CHIP_FAMILY_MASK = 0x0000ffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CHIP_FLAGS_MASK = 0xffff0000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CHIP_IS_MOBILITY = 0x00010000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CHIP_IS_IGP = 0x00020000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CHIP_HAS_CRTC2 = 0x00040000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Errata workarounds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum radeon_errata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CHIP_ERRATA_R300_CG = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CHIP_ERRATA_PLL_DELAY = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Monitor types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum radeon_montype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MT_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MT_CRT, /* CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MT_LCD, /* LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MT_DFP, /* DVI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MT_CTV, /* composite TV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MT_STV /* S-Video out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * DDC i2c ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum ddc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ddc_none,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ddc_monid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ddc_dvi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ddc_vga,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ddc_crt2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Connector types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum conn_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) conn_none,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) conn_proprietary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) conn_crt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) conn_DVI_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) conn_DVI_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * PLL infos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct pll_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ppll_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ppll_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int sclk, mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * This structure contains the various registers manipulated by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * driver for setting or restoring a mode. It's mostly copied from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * XFree's RADEONSaveRec structure. A few chip settings might still be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * tweaked without beeing reflected or saved in these registers though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct radeon_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 ovr_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 ovr_wid_left_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 ovr_wid_top_bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 ov0_scale_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 mpp_tb_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 mpp_gp_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 subpic_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 viph_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 i2c_cntl_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 gen_int_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 cap0_trig_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 cap1_trig_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 bus_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 surface_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 bios_5_scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Other registers to save for VT switches or driver load/unload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 dp_datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 rbbm_soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 clock_cntl_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 amcgpio_en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 amcgpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Surface/tiling registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 surf_lower_bound[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 surf_upper_bound[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 surf_info[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* CRTC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 crtc_gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 crtc_ext_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 dac_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 crtc_h_total_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 crtc_h_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 crtc_v_total_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 crtc_v_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 crtc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 crtc_offset_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 crtc_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 disp_merge_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 grph_buffer_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 crtc_more_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* CRTC2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 crtc2_gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 dac2_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 disp_output_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 disp_hw_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 disp2_merge_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 grph2_buffer_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 crtc2_h_total_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 crtc2_h_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 crtc2_v_total_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 crtc2_v_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 crtc2_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 crtc2_offset_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 crtc2_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Flat panel regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 fp_crtc_h_total_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 fp_crtc_v_total_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 fp_gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 fp2_gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 fp_h_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 fp2_h_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 fp_horz_stretch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 fp_panel_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 fp_v_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 fp2_v_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 fp_vert_stretch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 lvds_gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 lvds_pll_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 tmds_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 tmds_transmitter_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Computed values for PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 dot_clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int feedback_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* PLL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 ppll_div_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 ppll_ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 vclk_ecp_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 clk_cntl_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Computed values for PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 dot_clock_freq_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int feedback_div_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int post_div_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* PLL2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 p2pll_ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 p2pll_div_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 htotal_cntl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Palette */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int palette_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct panel_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int xres, yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int hOver_plus, hSync_width, hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int vOver_plus, vSync_width, vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int hAct_high, vAct_high, interlaced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int pwr_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int use_bios_dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int ref_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int post_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int fbk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct radeonfb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifdef CONFIG_FB_RADEON_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct radeon_i2c_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct radeonfb_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 ddc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct i2c_algo_bit_data algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enum radeon_pm_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) radeon_pm_none = 0, /* Nothing supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) radeon_pm_d2 = 0x00000001, /* Can do D2 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct radeonfb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct radeon_regs state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct radeon_regs init_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) char name[50];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned long mmio_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned long fb_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void __iomem *fb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long fb_local_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) void __iomem *bios_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int fp_bios_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct { u8 red, green, blue, pad; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) palette[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned long video_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long mapped_vram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int vram_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int vram_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int pitch, bpp, depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int has_CRTC2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int is_mobility;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int is_IGP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int reversed_DAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int reversed_TMDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct panel_info panel_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int mon1_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 *mon1_EDID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct fb_videomode *mon1_modedb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int mon1_dbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int mon2_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 *mon2_EDID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 dp_gui_master_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct pll_info pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 save_regs[100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int asleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int lock_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int dynclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int no_schedule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) enum radeon_pm_mode pm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) reinit_function_ptr reinit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Lock on register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Timer used for delayed LVDS operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct timer_list lvds_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 pending_lvds_gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #ifdef CONFIG_FB_RADEON_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct radeon_i2c_chan i2c[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * IO macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define INREG8(addr) readb((rinfo->mmio_base)+addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define INREG16(addr) readw((rinfo->mmio_base)+addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define INREG(addr) readl((rinfo->mmio_base)+addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Note about PLL register accesses:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * I have removed the spinlock on them on purpose. The driver now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * expects that it will only manipulate the PLL registers in normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * task environment, where radeon_msleep() will be called, protected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * by a semaphore (currently the console semaphore) so that no conflict
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * will happen on the PLL register index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * With the latest changes to the VT layer, this is guaranteed for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * calls except the actual drawing/blits which aren't supposed to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * the PLL registers anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * This is very important for the workarounds to work properly. The only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * possible exception to this rule is the call to unblank(), which may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * be done at irq time if an oops is in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) radeon_pll_errata_after_index_slow(rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (rinfo->errata & (CHIP_ERRATA_PLL_DELAY|CHIP_ERRATA_R300_CG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) radeon_pll_errata_after_data_slow(rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 __INPLL(struct radeonfb_info *rinfo, u32 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 val, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define INPLL(addr) __INPLL(rinfo, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) (readb(rinfo->bios_seg + (v) + 1) << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) (readb(rinfo->bios_seg + (v) + 1) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) (readb(rinfo->bios_seg + (v) + 2) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (readb(rinfo->bios_seg + (v) + 3) << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * Inline utilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static inline int round_div(int num, int den)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return (num + (den / 2)) / den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static inline int var_to_depth(const struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (var->bits_per_pixel != 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return var->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return (var->green.length == 5) ? 15 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static inline u32 radeon_get_dstbpp(u16 depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) switch (depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return DST_8BPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return DST_15BPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return DST_16BPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return DST_32BPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * 2D Engine helper routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) void radeon_engine_flush(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) void _radeon_engine_idle(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define radeon_engine_idle() _radeon_engine_idle(rinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* I2C Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* PM Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) extern const struct dev_pm_ops radeonfb_pci_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Monitor probe functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) extern void radeon_probe_screens(struct radeonfb_info *rinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) const char *monitor_layout, int ignore_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) extern int radeon_match_mode(struct radeonfb_info *rinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct fb_var_screeninfo *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) const struct fb_var_screeninfo *src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Accel functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) extern int radeonfb_sync(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Other functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int reg_only);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Backlight functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #ifdef CONFIG_FB_RADEON_BACKLIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #endif /* __RADEONFB_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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