Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  ATI Frame Buffer Device Driver Core Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)      *  Elements of the hardware specific atyfb_par structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) struct crtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	u32 vxres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	u32 vyres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	u32 xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	u32 yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	u32 h_tot_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u32 h_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u32 v_tot_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u32 v_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u32 vline_crnt_vline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u32 off_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32 gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u32 dp_pix_width;	/* acceleration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u32 dp_chain_mask;	/* acceleration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #ifdef CONFIG_FB_ATY_GENERIC_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32 horz_stretching;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 vert_stretching;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32 ext_vert_stretch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 shadow_h_tot_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 shadow_h_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 shadow_v_tot_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 shadow_v_sync_strt_wid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 lcd_gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 lcd_config_panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32 lcd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct aty_interrupt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int pan_display;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct pll_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int pll_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int pll_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int sclk, mclk, mclk_pm, xclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int ecp_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u16 unknown1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u16 PCLK_min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u16 PCLK_max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u16 unknown2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u16 ref_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u16 ref_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u16 unknown3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u16 MCLK_pwd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u16 MCLK_max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u16 XCLK_max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u16 SCLK_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) } __attribute__ ((packed)) PLL_BLOCK_MACH64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct pll_514 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u8 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u8 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) struct pll_18818 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 program_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 locationAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 period_in_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 post_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) struct pll_ct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u8 pll_ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u8 pll_gen_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 mclk_fb_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u8 mclk_fb_mult; /* 2 ro 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u8 sclk_fb_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u8 pll_vclk_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u8 vclk_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u8 vclk_fb_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u8 pll_ext_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u8 ext_vpll_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u8 spll_cntl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 dsp_config; /* Mach64 GTB DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 dsp_on_off; /* Mach64 GTB DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 dsp_loop_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 xclkpagefaultdelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 xclkmaxrasdelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u8 xclk_ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u8 xclk_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u8 mclk_post_div_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u8 xclk_post_div_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u8 vclk_post_div_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u8 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_FB_ATY_GENERIC_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 xres; /* use for LCD stretching/scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	for pll_ct.features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DONT_USE_SPLL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DONT_USE_XDLL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define USE_CPUCLK    0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define POWERDOWN_PLL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) union aty_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct pll_ct ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct pll_514 ibm514;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct pll_18818 ics2595;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)      *  The hardware parameters for each card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct atyfb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct { u8 red, green, blue; } palette[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	const struct aty_dac_ops *dac_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	const struct aty_pll_ops *pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	void __iomem *ati_regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	unsigned long clk_wr_offset; /* meaning overloaded, clock id by CT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct crtc crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	union aty_pll pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct pll_info pll_limits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u32 ref_clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u32 pll_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u32 mclk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32 xclk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u8 bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u8 ram_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u8 mem_refresh_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u16 pci_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 accel_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int blitter_may_be_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned fifo_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int asleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	int lock_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned long res_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned long res_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #ifdef __sparc__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct pci_mmap_map *mmap_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u8 mmaped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifdef CONFIG_FB_ATY_GENERIC_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	unsigned long bios_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned long bios_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned long lcd_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u16 lcd_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u16 lcd_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 lcd_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u16 lcd_refreshrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u16 lcd_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u16 lcd_hdisp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u16 lcd_hsync_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u16 lcd_hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u16 lcd_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u16 lcd_vdisp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u16 lcd_vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u16 lcd_right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u16 lcd_lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u16 lcd_hblank_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u16 lcd_vblank_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned long aux_start; /* auxiliary aperture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	unsigned long aux_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct aty_interrupt vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	spinlock_t int_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u32 mem_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct crtc saved_crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	union aty_pll saved_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)      *  ATI Mach64 features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define M64_HAS(feature)	((par)->features & (M64F_##feature))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define M64F_RESET_3D		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define M64F_MAGIC_FIFO		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define M64F_GTB_DSP		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define M64F_FIFO_32		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define M64F_SDRAM_MAGIC_PLL	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define M64F_MAGIC_POSTDIV	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define M64F_INTEGRATED		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define M64F_CT_BUS		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define M64F_VT_BUS		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define M64F_MOBIL_BUS		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define M64F_GX			0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define M64F_CT			0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define M64F_VT			0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define M64F_GT			0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define M64F_MAGIC_VRAM_SIZE	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define M64F_G3_PB_1_1		0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define M64F_G3_PB_1024x768	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define M64F_EXTRA_BRIGHT	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define M64F_LT_LCD_REGS	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define M64F_XL_DLL		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define M64F_MFB_FORCE_4	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define M64F_HW_TRIPLE		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define M64F_XL_MEM		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)      *  Register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline u32 aty_ld_le32(int regindex, const struct atyfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* Hack for bloc 1, should be cleanly optimized by compiler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (regindex >= 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		regindex -= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_ATARI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return in_le32(par->ati_regbase + regindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return readl(par->ati_regbase + regindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/* Hack for bloc 1, should be cleanly optimized by compiler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (regindex >= 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		regindex -= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #ifdef CONFIG_ATARI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	out_le32(par->ati_regbase + regindex, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	writel(val, par->ati_regbase + regindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline void aty_st_le16(int regindex, u16 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			       const struct atyfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Hack for bloc 1, should be cleanly optimized by compiler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (regindex >= 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		regindex -= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #ifdef CONFIG_ATARI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	out_le16(par->ati_regbase + regindex, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	writel(val, par->ati_regbase + regindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* Hack for bloc 1, should be cleanly optimized by compiler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (regindex >= 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		regindex -= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef CONFIG_ATARI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return in_8(par->ati_regbase + regindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return readb(par->ati_regbase + regindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Hack for bloc 1, should be cleanly optimized by compiler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (regindex >= 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		regindex -= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #ifdef CONFIG_ATARI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	out_8(par->ati_regbase + regindex, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	writeb(val, par->ati_regbase + regindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #if defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) defined (CONFIG_FB_ATY_BACKLIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) extern u32 aty_ld_lcd(int index, const struct atyfb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)      *  DAC operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct aty_dac_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	int (*set_dac) (const struct fb_info * info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		const union aty_pll * pll, u32 bpp, u32 accel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) extern const struct aty_dac_ops aty_dac_ct; /* Integrated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)      *  Clock operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct aty_pll_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	void (*set_pll)   (const struct fb_info * info, const union aty_pll * pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	void (*get_pll)   (const struct fb_info *info, union aty_pll * pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	int (*init_pll)   (const struct fb_info * info, union aty_pll * pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	void (*resume_pll)(const struct fb_info *info, union aty_pll *pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) extern const struct aty_pll_ops aty_pll_ct; /* Integrated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) extern const u8 aty_postdividers[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)      *  Hardware cursor support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) extern int aty_init_cursor(struct fb_info *info, struct fb_ops *atyfb_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)      *  Hardware acceleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static inline void wait_for_fifo(u16 entries, struct atyfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	unsigned fifo_space = par->fifo_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	while (entries > fifo_space) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		fifo_space = 16 - fls(aty_ld_le32(FIFO_STAT, par) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	par->fifo_space = fifo_space - entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static inline void wait_for_idle(struct atyfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	wait_for_fifo(16, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	while ((aty_ld_le32(GUI_STAT, par) & 1) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	par->blitter_may_be_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) extern void aty_reset_engine(struct atyfb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)