^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for AT91 LCD Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <video/of_videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <video/of_display_timing.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <video/videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <video/atmel_lcdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct atmel_lcdfb_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) bool have_alt_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bool have_hozval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bool have_intensity_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* LCD Controller info data structure, stored in device platform_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct atmel_lcdfb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct work_struct task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk *lcdc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct backlight_device *backlight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 bl_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 saved_lcdcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bool have_intensity_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct atmel_lcdfb_pdata pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct atmel_lcdfb_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct regulator *reg_lcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct atmel_lcdfb_power_ctrl_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* configurable parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ATMEL_LCDC_FIFO_SIZE 512 /* words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct atmel_lcdfb_config at91sam9261_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .have_hozval = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .have_intensity_bit = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct atmel_lcdfb_config at91sam9263_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .have_intensity_bit = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct atmel_lcdfb_config at91sam9g10_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .have_hozval = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct atmel_lcdfb_config at91sam9g45_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .have_alt_pixclock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct atmel_lcdfb_config at91sam9g45es_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct atmel_lcdfb_config at91sam9rl_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .have_intensity_bit = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) | ATMEL_LCDC_POL_POSITIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) | ATMEL_LCDC_ENA_PWMENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* some bl->props field just changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int atmel_bl_update_status(struct backlight_device *bl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int power = sinfo->bl_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int brightness = bl->props.brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* REVISIT there may be a meaningful difference between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * fb_blank and power ... there seem to be some cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * this doesn't handle correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (bl->props.fb_blank != sinfo->bl_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) power = bl->props.fb_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else if (bl->props.power != sinfo->bl_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) power = bl->props.power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (brightness < 0 && power == FB_BLANK_UNBLANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else if (power != FB_BLANK_UNBLANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) brightness = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (contrast_ctr & ATMEL_LCDC_POL_POSITIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) brightness ? contrast_ctr : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int atmel_bl_get_brightness(struct backlight_device *bl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct backlight_ops atmel_lcdc_bl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .update_status = atmel_bl_update_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .get_brightness = atmel_bl_get_brightness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void init_backlight(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct backlight_properties props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct backlight_device *bl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sinfo->bl_power = FB_BLANK_UNBLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (sinfo->backlight)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) memset(&props, 0, sizeof(struct backlight_properties));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) props.type = BACKLIGHT_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) props.max_brightness = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) &atmel_lcdc_bl_ops, &props);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (IS_ERR(bl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PTR_ERR(bl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sinfo->backlight = bl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bl->props.power = FB_BLANK_UNBLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bl->props.fb_blank = FB_BLANK_UNBLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bl->props.brightness = atmel_bl_get_brightness(bl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void exit_backlight(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!sinfo->backlight)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (sinfo->backlight->ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sinfo->backlight->props.power = FB_BLANK_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sinfo->backlight->ops->update_status(sinfo->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) backlight_device_unregister(sinfo->backlight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void init_backlight(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void exit_backlight(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void init_contrast(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* contrast pwm can be 'inverted' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (pdata->lcdcon_pol_negative)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* have some default contrast/backlight settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (pdata->lcdcon_is_backlight)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) init_backlight(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline void atmel_lcdfb_power_control(struct atmel_lcdfb_info *sinfo, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (pdata->atmel_lcdfb_power_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pdata->atmel_lcdfb_power_control(pdata, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else if (sinfo->reg_lcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = regulator_enable(sinfo->reg_lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(&sinfo->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "lcd regulator enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = regulator_disable(sinfo->reg_lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(&sinfo->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "lcd regulator disable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct fb_fix_screeninfo atmel_lcdfb_fix __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .visual = FB_VISUAL_TRUECOLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .xpanstep = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .ypanstep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .ywrapstep = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .accel = FB_ACCEL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static unsigned long compute_hozval(struct atmel_lcdfb_info *sinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long xres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long lcdcon2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!sinfo->config->have_hozval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) lcdcon2 = lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) value = xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* STN display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) value *= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) value = DIV_ROUND_UP(value, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) value = DIV_ROUND_UP(value, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Turn off the LCD controller and the DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Wait for the LCDC core to become idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) atmel_lcdfb_stop_nowait(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Wait for DMA engine to become idle... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) lcdc_writel(sinfo, ATMEL_LCDC_DMACON, pdata->default_dmacon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) (pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) | ATMEL_LCDC_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void atmel_lcdfb_update_dma(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct atmel_lcdfb_info *sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct fb_fix_screeninfo *fix = &info->fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dma_addr = (fix->smem_start + var->yoffset * fix->line_length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) + var->xoffset * info->var.bits_per_pixel / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dma_addr &= ~3UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Set framebuffer DMA base address and pixel offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct fb_info *info = sinfo->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dma_free_wc(info->device, info->fix.smem_len, info->screen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) info->fix.smem_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @sinfo: the frame buffer to allocate memory for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * This function is called only from the atmel_lcdfb_probe()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * so no locking by fb_info->mm_lock around smem_len setting is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct fb_info *info = sinfo->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned int smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) smem_len = (var->xres_virtual * var->yres_virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * ((var->bits_per_pixel + 7) / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) info->fix.smem_len = max(smem_len, sinfo->smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) info->screen_base = dma_alloc_wc(info->device, info->fix.smem_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (dma_addr_t *)&info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) memset(info->screen_base, 0, info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct fb_videomode varfbmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct fb_videomode *fbmode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) fb_var_to_videomode(&varfbmode, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (fbmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) fb_videomode_to_var(var, fbmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return fbmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * atmel_lcdfb_check_var - Validates a var passed in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * @var: frame buffer variable screen structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @info: frame buffer structure that represents a single frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Checks to see if the hardware supports the state requested by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * var passed in. This function does not alter the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * state!!! This means the data stored in struct fb_info and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * struct atmel_lcdfb_info do not change. This includes the var
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * inside of struct fb_info. Do NOT change these. This function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * can be called on its own if we intent to only test a mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * not actually set it. The stuff in modedb.c is a example of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * this. If the var passed in is slightly off by what the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * hardware can support then we alter the var PASSED in to what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * we can do. If the hardware doesn't support mode change a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * -EINVAL will be returned by the upper layers. You don't need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * to implement this function then. If you hardware doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * support changing the resolution then this function is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * needed. In this case the driver would just provide a var that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * represents the static state the screen is in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Returns negative errno on error, or zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct device *dev = info->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct atmel_lcdfb_info *sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long clk_value_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_dbg(dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!(var->pixclock && var->bits_per_pixel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* choose a suitable mode if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!atmel_lcdfb_choose_mode(var, info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(dev, "needed value not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Do not allow to have real resoulution larger than virtual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (var->xres > var->xres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) var->xres_virtual = var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (var->yres > var->yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) var->yres_virtual = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Force same alignment for each line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) var->xres = (var->xres + 3) & ~3UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) var->transp.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) var->transp.offset = var->transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) var->xoffset = var->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int smem_len = (var->xres_virtual * var->yres_virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * ((var->bits_per_pixel + 7) / 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (smem_len > info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(dev, "Frame buffer is too small (%u) for screen size (need at least %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) info->fix.smem_len, smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Saturate vertical and horizontal timings at maximum values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) var->vsync_len = min_t(u32, var->vsync_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) var->upper_margin = min_t(u32, var->upper_margin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) var->lower_margin = min_t(u32, var->lower_margin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ATMEL_LCDC_VFP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) var->right_margin = min_t(u32, var->right_margin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) var->hsync_len = min_t(u32, var->hsync_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) var->left_margin = min_t(u32, var->left_margin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ATMEL_LCDC_HBP + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Some parameters can't be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) var->vsync_len = max_t(u32, var->vsync_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) var->right_margin = max_t(u32, var->right_margin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) var->hsync_len = max_t(u32, var->hsync_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) var->left_margin = max_t(u32, var->left_margin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) switch (var->bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) var->red.offset = var->green.offset = var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) var->red.length = var->green.length = var->blue.length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) = var->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Older SOCs use IBGR:555 rather than BGR:565. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (sinfo->config->have_intensity_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) var->green.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) var->green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* RGB:5X5 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) var->red.offset = var->green.length + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* BGR:5X5 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) var->red.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) var->blue.offset = var->green.length + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) var->green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) var->red.length = var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) var->transp.offset = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) var->transp.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* RGB:888 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) var->red.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* BGR:888 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) var->red.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) var->blue.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) var->red.length = var->green.length = var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_err(dev, "color depth %d not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * LCD reset sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) atmel_lcdfb_stop(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) atmel_lcdfb_start(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * atmel_lcdfb_set_par - Alters the hardware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * @info: frame buffer structure that represents a single frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * Using the fb_var_screeninfo in fb_info we set the resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * of the this particular framebuffer. This function alters the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * not alter var in fb_info since we are using that data. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * means we depend on the data in var inside fb_info to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * supported by the hardware. atmel_lcdfb_check_var is always called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * before atmel_lcdfb_set_par to ensure this. Again if you can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * change the resolution you don't need this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int atmel_lcdfb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct atmel_lcdfb_info *sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned long hozval_linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned long clk_value_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned long bits_per_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned long pix_factor = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_dbg(info->device, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) info->var.xres, info->var.yres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) info->var.xres_virtual, info->var.yres_virtual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) atmel_lcdfb_stop_nowait(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (info->var.bits_per_pixel == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) info->fix.visual = FB_VISUAL_MONO01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) else if (info->var.bits_per_pixel <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) info->fix.visual = FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Re-initialize the DMA engine... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_dbg(info->device, " * update DMA engine\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) atmel_lcdfb_update_dma(info, &info->var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* ...set frame size and burst length = 8 words (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Now, the LCDC core... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Set pixel clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (sinfo->config->have_alt_pixclock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pix_factor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (value < pix_factor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_notice(info->device, "Bypassing pixel clock divider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) value = (value / pix_factor) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) value << ATMEL_LCDC_CLKVAL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) info->var.pixclock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_dbg(info->device, " updated pixclk: %lu KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PICOS2KHZ(info->var.pixclock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Initialize control register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) value = pdata->default_lcdcon2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) value |= ATMEL_LCDC_INVLINE_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) value |= ATMEL_LCDC_INVFRAME_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) switch (info->var.bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) case 15: fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) default: BUG(); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Vertical timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) value |= info->var.lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Horizontal timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) value |= (info->var.left_margin - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Horizontal value (aka line size) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) hozval_linesz = compute_hozval(sinfo, info->var.xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Display size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) value |= info->var.yres - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* FIFO Threshold: Use formula from data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Toggle LCD_MODE every frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Enable FIFO & DMA errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* ...wait for DMA engine to become idle... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) atmel_lcdfb_start(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_dbg(info->device, " * DONE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) chan &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) chan >>= 16 - bf->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return chan << bf->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * atmel_lcdfb_setcolreg - Optional function. Sets a color register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * @regno: Which register in the CLUT we are programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * @red: The red value which can be up to 16 bits wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * @green: The green value which can be up to 16 bits wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * @blue: The blue value which can be up to 16 bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * @transp: If supported the alpha value which can be up to 16 bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * @info: frame buffer info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * Set a single color register. The values supplied have a 16 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * magnitude which needs to be scaled in this function for the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * Things to take into consideration are how many color registers, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * any, are supported with the current color visual. With truecolor mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * no color palettes are supported. Here a pseudo palette is created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * which we store the value in pseudo_palette in struct fb_info. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * pseudocolor mode we have a limited color palette. To deal with this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * we can program what color is displayed for a particular pixel value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * DirectColor is similar in that we can program each color field. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * we have a static colormap we don't need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * Returns negative errno on error, or zero on success. In an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * ideal world, this would have been the case, but as it turns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * out, the other drivers return 1 on failure, so that's what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * we're going to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned int green, unsigned int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct atmel_lcdfb_info *sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 *pal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (info->var.grayscale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) red = green = blue = (19595 * red + 38470 * green
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) + 7471 * blue) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) switch (info->fix.visual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case FB_VISUAL_TRUECOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (regno < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pal = info->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) val = chan_to_field(red, &info->var.red);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) val |= chan_to_field(green, &info->var.green);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val |= chan_to_field(blue, &info->var.blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pal[regno] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case FB_VISUAL_PSEUDOCOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (regno < 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (sinfo->config->have_intensity_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* old style I+BGR:555 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) val = ((red >> 11) & 0x001f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) val |= ((green >> 6) & 0x03e0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) val |= ((blue >> 1) & 0x7c00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * TODO: intensity bit. Maybe something like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * ~(red[10] ^ green[10] ^ blue[10]) & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* new style BGR:565 / RGB:565 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) val = ((blue >> 11) & 0x001f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val |= ((red >> 0) & 0xf800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) val = ((red >> 11) & 0x001f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) val |= ((blue >> 0) & 0xf800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) val |= ((green >> 5) & 0x07e0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case FB_VISUAL_MONO01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (regno < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) val = (regno == 0) ? 0x00 : 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dev_dbg(info->device, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) atmel_lcdfb_update_dma(info, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct atmel_lcdfb_info *sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) switch (blank_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case FB_BLANK_UNBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case FB_BLANK_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) atmel_lcdfb_start(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case FB_BLANK_VSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case FB_BLANK_HSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case FB_BLANK_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) atmel_lcdfb_stop(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* let fbcon do a soft blank for us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static const struct fb_ops atmel_lcdfb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .fb_check_var = atmel_lcdfb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .fb_set_par = atmel_lcdfb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .fb_setcolreg = atmel_lcdfb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .fb_blank = atmel_lcdfb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .fb_pan_display = atmel_lcdfb_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct fb_info *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct atmel_lcdfb_info *sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (status & ATMEL_LCDC_UFLWI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_warn(info->device, "FIFO underflow %#x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* reset DMA and FIFO to avoid screen shifting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) schedule_work(&sinfo->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * LCD controller task (to reset the LCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void atmel_lcdfb_task(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct atmel_lcdfb_info *sinfo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) container_of(work, struct atmel_lcdfb_info, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) atmel_lcdfb_reset(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct fb_info *info = sinfo->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_info(info->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) "%luKiB frame buffer at %08lx (mapped at %p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) (unsigned long)info->fix.smem_len / 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) (unsigned long)info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* Allocate colormap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret = fb_alloc_cmap(&info->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dev_err(info->device, "Alloc color map failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) clk_prepare_enable(sinfo->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) clk_prepare_enable(sinfo->lcdc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) clk_disable_unprepare(sinfo->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) clk_disable_unprepare(sinfo->lcdc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct of_device_id atmel_lcdfb_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) { .compatible = "atmel,at91sam9261-lcdc" , .data = &at91sam9261_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { .compatible = "atmel,at91sam9263-lcdc" , .data = &at91sam9263_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { .compatible = "atmel,at91sam9g10-lcdc" , .data = &at91sam9g10_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) { .compatible = "atmel,at91sam9g45-lcdc" , .data = &at91sam9g45_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) { .compatible = "atmel,at91sam9g45es-lcdc" , .data = &at91sam9g45es_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) { .compatible = "atmel,at91sam9rl-lcdc" , .data = &at91sam9rl_config, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) MODULE_DEVICE_TABLE(of, atmel_lcdfb_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static const char *atmel_lcdfb_wiring_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) [ATMEL_LCDC_WIRING_BGR] = "BRG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) [ATMEL_LCDC_WIRING_RGB] = "RGB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int atmel_lcdfb_get_of_wiring_modes(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) const char *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) err = of_property_read_string(np, "atmel,lcd-wiring-mode", &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return ATMEL_LCDC_WIRING_BGR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) for (i = 0; i < ARRAY_SIZE(atmel_lcdfb_wiring_modes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!strcasecmp(mode, atmel_lcdfb_wiring_modes[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static void atmel_lcdfb_power_control_gpio(struct atmel_lcdfb_pdata *pdata, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct atmel_lcdfb_power_ctrl_gpio *og;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) list_for_each_entry(og, &pdata->pwr_gpios, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) gpiod_set_value(og->gpiod, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct fb_info *info = sinfo->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct device *dev = &sinfo->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct device_node *np =dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct device_node *display_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct atmel_lcdfb_power_ctrl_gpio *og;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) bool is_gpio_power = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct fb_videomode fb_vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct videomode vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) sinfo->config = (struct atmel_lcdfb_config*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) of_match_device(atmel_lcdfb_dt_ids, dev)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) display_np = of_parse_phandle(np, "display", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (!display_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_err(dev, "failed to find display phandle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = of_property_read_u32(display_np, "bits-per-pixel", &var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dev_err(dev, "failed to get property bits-per-pixel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = of_property_read_u32(display_np, "atmel,guard-time", &pdata->guard_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_err(dev, "failed to get property atmel,guard-time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret = of_property_read_u32(display_np, "atmel,lcdcon2", &pdata->default_lcdcon2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dev_err(dev, "failed to get property atmel,lcdcon2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = of_property_read_u32(display_np, "atmel,dmacon", &pdata->default_dmacon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_err(dev, "failed to get property bits-per-pixel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) INIT_LIST_HEAD(&pdata->pwr_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) for (i = 0; i < gpiod_count(dev, "atmel,power-control"); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) gpiod = devm_gpiod_get_index(dev, "atmel,power-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) i, GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (IS_ERR(gpiod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) og = devm_kzalloc(dev, sizeof(*og), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!og)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) og->gpiod = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) is_gpio_power = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret = gpiod_direction_output(gpiod, gpiod_is_active_low(gpiod));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_err(dev, "set direction output gpio atmel,power-control[%d] failed\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) list_add(&og->list, &pdata->pwr_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (is_gpio_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) pdata->atmel_lcdfb_power_control = atmel_lcdfb_power_control_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = atmel_lcdfb_get_of_wiring_modes(display_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) dev_err(dev, "invalid atmel,lcd-wiring-mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) pdata->lcd_wiring_mode = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pdata->lcdcon_is_backlight = of_property_read_bool(display_np, "atmel,lcdcon-backlight");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) pdata->lcdcon_pol_negative = of_property_read_bool(display_np, "atmel,lcdcon-backlight-inverted");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dev_err(dev, "failed to get videomode from DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ret = fb_videomode_from_videomode(&vm, &fb_vm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) goto put_display_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) fb_add_videomode(&fb_vm, &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) put_display_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) of_node_put(display_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static int __init atmel_lcdfb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct atmel_lcdfb_info *sinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct resource *regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct resource *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct fb_modelist *modelist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) dev_dbg(dev, "%s BEGIN\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) sinfo->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) sinfo->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) INIT_LIST_HEAD(&info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (!pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dev_err(dev, "cannot get default configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) goto free_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = atmel_lcdfb_of_init(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) goto free_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!sinfo->config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) goto free_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) sinfo->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (IS_ERR(sinfo->reg_lcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) sinfo->reg_lcd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) info->flags = FBINFO_DEFAULT | FBINFO_PARTIAL_PAN_OK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) info->pseudo_palette = sinfo->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) info->fbops = &atmel_lcdfb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) info->fix = atmel_lcdfb_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) strcpy(info->fix.id, sinfo->pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Enable LCDC Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) sinfo->bus_clk = clk_get(dev, "hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (IS_ERR(sinfo->bus_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret = PTR_ERR(sinfo->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) goto free_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (IS_ERR(sinfo->lcdc_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret = PTR_ERR(sinfo->lcdc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) goto put_bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) atmel_lcdfb_start_clock(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) modelist = list_first_entry(&info->modelist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct fb_modelist, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) fb_videomode_to_var(&info->var, &modelist->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) atmel_lcdfb_check_var(&info->var, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev_err(dev, "resources unusable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) goto stop_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) sinfo->irq_base = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (sinfo->irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ret = sinfo->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) goto stop_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Initialize video memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* use a pre-allocated memory buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) info->fix.smem_start = map->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) info->fix.smem_len = resource_size(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!request_mem_region(info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) info->fix.smem_len, pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) goto stop_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) info->screen_base = ioremap_wc(info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (!info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto release_intmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * Don't clear the framebuffer -- someone may have set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * up a splash image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* allocate memory buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ret = atmel_lcdfb_alloc_video_memory(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) goto stop_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* LCDC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) info->fix.mmio_start = regs->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) info->fix.mmio_len = resource_size(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (!request_mem_region(info->fix.mmio_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) info->fix.mmio_len, pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) goto free_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (!sinfo->mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_err(dev, "cannot map LCDC registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) goto release_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Initialize PWM for contrast or backlight ("off") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) init_contrast(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) dev_err(dev, "request_irq failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) goto unmap_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Some operations on the LCDC might sleep and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * require a preemptible task context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) INIT_WORK(&sinfo->task, atmel_lcdfb_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = atmel_lcdfb_init_fbinfo(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_err(dev, "init fbinfo failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) goto unregister_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = atmel_lcdfb_set_par(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dev_err(dev, "set par failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) goto unregister_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_set_drvdata(dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * Tell the world that we're ready to go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret = register_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dev_err(dev, "failed to register framebuffer device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) goto reset_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* Power up the LCDC screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) atmel_lcdfb_power_control(sinfo, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) reset_drvdata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unregister_irqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) cancel_work_sync(&sinfo->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) free_irq(sinfo->irq_base, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) unmap_mmio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) exit_backlight(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) iounmap(sinfo->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) release_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) free_fb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) atmel_lcdfb_free_video_memory(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) release_intmem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) release_mem_region(info->fix.smem_start, info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) stop_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) atmel_lcdfb_stop_clock(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) clk_put(sinfo->lcdc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) put_bus_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) clk_put(sinfo->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) free_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dev_dbg(dev, "%s FAILED\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct fb_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct atmel_lcdfb_info *sinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (!info || !info->par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) cancel_work_sync(&sinfo->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) exit_backlight(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) atmel_lcdfb_power_control(sinfo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) atmel_lcdfb_stop_clock(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) clk_put(sinfo->lcdc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) clk_put(sinfo->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) free_irq(sinfo->irq_base, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) iounmap(sinfo->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) release_mem_region(info->fix.smem_start, info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) atmel_lcdfb_free_video_memory(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct fb_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct atmel_lcdfb_info *sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * We don't want to handle interrupts while the clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * stopped. It may take forever.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) atmel_lcdfb_power_control(sinfo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) atmel_lcdfb_stop(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) atmel_lcdfb_stop_clock(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int atmel_lcdfb_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct fb_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct atmel_lcdfb_info *sinfo = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) atmel_lcdfb_start_clock(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) atmel_lcdfb_start(sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) atmel_lcdfb_power_control(sinfo, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* Enable FIFO & DMA errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define atmel_lcdfb_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define atmel_lcdfb_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static struct platform_driver atmel_lcdfb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .remove = __exit_p(atmel_lcdfb_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .suspend = atmel_lcdfb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .resume = atmel_lcdfb_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .name = "atmel_lcdfb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .of_match_table = of_match_ptr(atmel_lcdfb_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) module_platform_driver_probe(atmel_lcdfb_driver, atmel_lcdfb_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) MODULE_DESCRIPTION("AT91 LCD Controller framebuffer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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