^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/video/asiliantfb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * frame buffer driver for Asiliant 69000 chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2001-2003 Saito.K & Jeanne
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * from driver/video/chipsfb.c and,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * drivers/video/asiliantfb.c -- frame buffer device for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: apc@agelectronics.co.uk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2000 AG Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Note: the data sheets don't seem to be available from Asiliant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * They are available by searching developer.intel.com, but are not otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * linked to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This driver should be portable with minimal effort to the 69000 display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * chip, and to the twin-display mode of the 69030.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Derived from the CT65550 driver chipsfb.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Copyright (C) 1998 Paul Mackerras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ...which was derived from the Powermac "chips" driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Copyright (C) 1997 Fabio Riccardi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * And from the frame buffer device for Open Firmware-initialized devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Copyright (C) 1997 Geert Uytterhoeven.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Built in clock of the 69030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const unsigned Fref = 14318180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define mmio_base (p->screen_base + 0x400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define mm_write_ind(num, val, ap, dp) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void mm_write_xr(struct fb_info *p, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mm_write_ind(reg, data, 0x7ac, 0x7ad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define write_xr(num, val) mm_write_xr(p, num, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void mm_write_fr(struct fb_info *p, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mm_write_ind(reg, data, 0x7a0, 0x7a1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define write_fr(num, val) mm_write_fr(p, num, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void mm_write_cr(struct fb_info *p, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mm_write_ind(reg, data, 0x7a8, 0x7a9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define write_cr(num, val) mm_write_cr(p, num, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void mm_write_gr(struct fb_info *p, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mm_write_ind(reg, data, 0x79c, 0x79d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define write_gr(num, val) mm_write_gr(p, num, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void mm_write_sr(struct fb_info *p, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mm_write_ind(reg, data, 0x788, 0x789);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define write_sr(num, val) mm_write_sr(p, num, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void mm_write_ar(struct fb_info *p, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) readb(mmio_base + 0x7b4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mm_write_ind(reg, data, 0x780, 0x780);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define write_ar(num, val) mm_write_ar(p, num, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int asiliantfb_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int asiliantfb_set_par(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u_int transp, struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct fb_ops asiliantfb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .fb_check_var = asiliantfb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .fb_set_par = asiliantfb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .fb_setcolreg = asiliantfb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Calculate the ratios for the dot clocks without using a single long long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned pixclock = *ppixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned Ftarget = 1000000 * (1000000 / pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned best_error = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned best_m = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) best_n = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned char divisor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Calculate the frequency required. This is hard enough. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ratio = 1000000 / pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) remainder = 1000000 % pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) while (Ftarget < 100000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) divisor += 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) Ftarget <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ratio = Ftarget / Fref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) remainder = Ftarget % Fref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * together with 3 <= n <= 257. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (n = 3; n <= 257; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned m = n * ratio + (n * remainder) / Fref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* 3 <= m <= 257 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (m >= 3 && m <= 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned new_error = Ftarget * n >= Fref * m ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (new_error < best_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) best_n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) best_m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) best_error = new_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* But if VLD = 4, then 4m <= 1028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else if (m <= 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* remember there are still only 8-bits of precision in m, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * avoid over-optimistic error calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned new_error = Ftarget * n >= Fref * (m & ~3) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (new_error < best_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) best_n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) best_m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) best_error = new_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (best_m > 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) divisor |= 4; /* or set VCO loop divide to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *dclk2_m = best_m - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *dclk2_n = best_n - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *dclk2_div = divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *ppixclock = pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void asiliant_set_timing(struct fb_info *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned hd = p->var.xres / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned hs = (p->var.xres + p->var.right_margin) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned vd = p->var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned vs = p->var.yres + p->var.lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) write_fr(0x01, 0x02); /* LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) write_fr(0x01, 0x01); /* CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) write_cr(0x11, (ve - 1) & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) write_cr(0x00, (ht - 5) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) write_cr(0x01, hd - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) write_cr(0x02, hd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) write_cr(0x04, hs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) write_cr(0x3c, (ht - 1) & 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) write_cr(0x06, (vt - 2) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) write_cr(0x30, (vt - 2) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) write_cr(0x07, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) write_cr(0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) write_cr(0x09, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) write_cr(0x10, (vs - 1) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) write_cr(0x32, ((vs - 1) >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) write_cr(0x12, (vd - 1) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) write_cr(0x31, ((vd - 1) & 0xf00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) write_cr(0x13, wd & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) write_cr(0x41, (wd & 0xf00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) write_cr(0x15, (vs - 1) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) write_cr(0x33, ((vs - 1) >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) write_cr(0x38, ((ht - 5) & 0x100) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) write_cr(0x16, (vt - 1) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) write_cr(0x18, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (p->var.xres == 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writeb(0xc7, mmio_base + 0x784); /* set misc output reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writeb(0x07, mmio_base + 0x784); /* set misc output reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int asiliantfb_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct fb_info *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long Ftarget, ratio, remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!var->pixclock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ratio = 1000000 / var->pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) remainder = 1000000 % var->pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* First check the constraint that the maximum post-VCO divisor is 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * and the maximum Fvco is 220MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (Ftarget > 220000000 || Ftarget < 3125000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) var->xres_virtual = var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) var->yres_virtual = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (var->bits_per_pixel == 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) var->red.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) var->red.length = var->blue.length = var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else if (var->bits_per_pixel == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (var->red.offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) var->green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) var->green.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) var->green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) var->red.length = var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else if (var->bits_per_pixel == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) var->red.offset = var->green.offset = var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) var->red.length = var->green.length = var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int asiliantfb_set_par(struct fb_info *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 dclk2_m; /* Holds m-2 value for register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 dclk2_n; /* Holds n-2 value for register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 dclk2_div; /* Holds divisor bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Set pixclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Set color depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (p->var.bits_per_pixel == 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) write_xr(0x81, 0x16); /* 24 bit packed color mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) write_xr(0x82, 0x00); /* Disable palettes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) write_xr(0x20, 0x20); /* 24 bit blitter mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else if (p->var.bits_per_pixel == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (p->var.red.offset == 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) write_xr(0x81, 0x15); /* 16 bit color mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) write_xr(0x81, 0x14); /* 15 bit color mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) write_xr(0x82, 0x00); /* Disable palettes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) write_xr(0x20, 0x10); /* 16 bit blitter mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } else if (p->var.bits_per_pixel == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) write_xr(0x0a, 0x02); /* Linear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) write_xr(0x81, 0x12); /* 8 bit color mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) write_xr(0x82, 0x00); /* Graphics gamma enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) write_xr(0x20, 0x00); /* 8 bit blitter mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) write_xr(0xc4, dclk2_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) write_xr(0xc5, dclk2_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) write_xr(0xc7, dclk2_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Set up the CR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) asiliant_set_timing(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u_int transp, struct fb_info *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (regno > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) red >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) green >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) blue >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Set hardware palete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) writeb(regno, mmio_base + 0x790);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writeb(red, mmio_base + 0x791);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writeb(green, mmio_base + 0x791);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writeb(blue, mmio_base + 0x791);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (regno < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) switch(p->var.red.offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case 10: /* RGB 555 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ((u32 *)(p->pseudo_palette))[regno] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ((red & 0xf8) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ((green & 0xf8) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ((blue & 0xf8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case 11: /* RGB 565 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ((u32 *)(p->pseudo_palette))[regno] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ((red & 0xf8) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ((green & 0xfc) << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ((blue & 0xf8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case 16: /* RGB 888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ((u32 *)(p->pseudo_palette))[regno] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (red << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) (green << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) (blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct chips_init_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct chips_init_reg chips_init_sr[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x00, 0x03}, /* Reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x01, 0x01}, /* Clocking mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x02, 0x0f}, /* Plane mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x04, 0x0e} /* Memory mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct chips_init_reg chips_init_gr[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x03, 0x00}, /* Data rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x05, 0x00}, /* Graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x06, 0x01}, /* Miscellaneous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x08, 0x00} /* Bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct chips_init_reg chips_init_ar[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x10, 0x01}, /* Mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x11, 0x00}, /* Overscan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x12, 0x0f}, /* Memory plane enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x13, 0x00} /* Horizontal pixel panning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct chips_init_reg chips_init_cr[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x0c, 0x00}, /* Start address high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x0d, 0x00}, /* Start address low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x40, 0x00}, /* Extended Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x41, 0x00}, /* Extended Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x14, 0x00}, /* Underline location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x17, 0xe3}, /* CRT mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x70, 0x00} /* Interlace control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct chips_init_reg chips_init_fr[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x01, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x03, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x08, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x0a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x18, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x1e, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x40, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x41, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x48, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x4d, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x4e, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x0b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x21, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x22, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x23, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x20, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x34, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x24, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x25, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x27, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x26, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x37, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x33, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x35, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x36, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x31, 0xea},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x32, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x30, 0xdf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x10, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x11, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x12, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x13, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x16, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x17, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x1a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct chips_init_reg chips_init_xr[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0xce, 0x00}, /* set default memory clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0xcc, 200 }, /* MCLK ratio M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0xcd, 18 }, /* MCLK ratio N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0xce, 0x90}, /* MCLK divisor = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0xc4, 209 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0xc5, 118 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0xc7, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0xcf, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x09, 0x01}, /* IO Control - CRT controller extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x0a, 0x02}, /* Frame buffer mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x0b, 0x01}, /* PCI burst write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x40, 0x03}, /* Memory access control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x80, 0x82}, /* Pixel pipeline configuration 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x81, 0x12}, /* Pixel pipeline configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x82, 0x08}, /* Pixel pipeline configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0xd0, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0xd1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void chips_hw_init(struct fb_info *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) write_xr(0x81, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) write_xr(0x82, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) write_xr(0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Enable video output in attribute index register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writeb(0x20, mmio_base + 0x780);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct fb_fix_screeninfo asiliantfb_fix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .id = "Asiliant 69000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .visual = FB_VISUAL_PSEUDOCOLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .accel = FB_ACCEL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .line_length = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .smem_len = 0x200000, /* 2MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct fb_var_screeninfo asiliantfb_var = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .xres_virtual = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .yres_virtual = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .bits_per_pixel = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .red = { .length = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .green = { .length = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .blue = { .length = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .height = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .width = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .vmode = FB_VMODE_NONINTERLACED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .pixclock = 39722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .left_margin = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .right_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .upper_margin = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .lower_margin = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .hsync_len = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .vsync_len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int init_asiliant(struct fb_info *p, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) p->fix = asiliantfb_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) p->fix.smem_start = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) p->var = asiliantfb_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) p->fbops = &asiliantfb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) p->flags = FBINFO_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) err = fb_alloc_cmap(&p->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) printk(KERN_ERR "C&T 69000 fb failed to alloc cmap memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) err = register_framebuffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) printk(KERN_ERR "C&T 69000 framebuffer failed to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) fb_dealloc_cmap(&p->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) fb_info(p, "Asiliant 69000 frame buffer (%dK RAM detected)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) p->fix.smem_len / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) writeb(0xff, mmio_base + 0x78c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) chips_hw_init(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int asiliantfb_pci_init(struct pci_dev *dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned long addr, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct fb_info *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) addr = pci_resource_start(dp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) size = pci_resource_len(dp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (addr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!request_mem_region(addr, size, "asiliantfb"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) release_mem_region(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) p->pseudo_palette = p->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) p->par = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) p->screen_base = ioremap(addr, 0x800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (p->screen_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) release_mem_region(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) framebuffer_release(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pci_write_config_dword(dp, 4, 0x02800083);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) writeb(3, p->screen_base + 0x400784);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) err = init_asiliant(p, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) iounmap(p->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) release_mem_region(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) framebuffer_release(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pci_set_drvdata(dp, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void asiliantfb_remove(struct pci_dev *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct fb_info *p = pci_get_drvdata(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unregister_framebuffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fb_dealloc_cmap(&p->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) iounmap(p->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) framebuffer_release(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const struct pci_device_id asiliantfb_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct pci_driver asiliantfb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .name = "asiliantfb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .id_table = asiliantfb_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .probe = asiliantfb_pci_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .remove = asiliantfb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int __init asiliantfb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (fb_get_options("asiliantfb", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return pci_register_driver(&asiliantfb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) module_init(asiliantfb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void __exit asiliantfb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pci_unregister_driver(&asiliantfb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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