^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/amifb.c -- Amiga builtin chipset frame buffer device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1995-2003 Geert Uytterhoeven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * with work by Roman Zippel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is based on the Atari frame buffer device (atafb.c):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 1994 Martin Schaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Roman Hodek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * with work by Andreas Schwab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Guenther Kelleter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * and on the original Amiga console driver (amicon.c):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright (C) 1993 Hamish Macdonald
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Greg Harp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Copyright (C) 1994 David Carter [carter@compsci.bristol.ac.uk]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * with work by William Rucklidge (wjr@cs.cornell.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Geert Uytterhoeven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Jes Sorensen (jds@kom.auc.dk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - 24 Jul 96: Copper generates now vblank interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * VESA Power Saving Protocol is fully implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - 14 Jul 96: Rework and hopefully last ECS bugs fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - 7 Mar 96: Hardware sprite support by Roman Zippel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * - 18 Feb 96: OCS and ECS support by Roman Zippel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Hardware functions completely rewritten
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * - 2 Dec 95: AGA version by Geert Uytterhoeven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <asm/amigahw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm/amigaints.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "c2p.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #if !defined(CONFIG_FB_AMIGA_OCS) && !defined(CONFIG_FB_AMIGA_ECS) && !defined(CONFIG_FB_AMIGA_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CONFIG_FB_AMIGA_OCS /* define at least one fb driver, this will change later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #if !defined(CONFIG_FB_AMIGA_OCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define IS_OCS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #elif defined(CONFIG_FB_AMIGA_ECS) || defined(CONFIG_FB_AMIGA_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define IS_OCS (chipset == TAG_OCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define CONFIG_FB_AMIGA_OCS_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define IS_OCS (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #if !defined(CONFIG_FB_AMIGA_ECS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # define IS_ECS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #elif defined(CONFIG_FB_AMIGA_OCS) || defined(CONFIG_FB_AMIGA_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define IS_ECS (chipset == TAG_ECS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define CONFIG_FB_AMIGA_ECS_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define IS_ECS (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #if !defined(CONFIG_FB_AMIGA_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define IS_AGA (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #elif defined(CONFIG_FB_AMIGA_OCS) || defined(CONFIG_FB_AMIGA_ECS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define IS_AGA (chipset == TAG_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define CONFIG_FB_AMIGA_AGA_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define IS_AGA (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define DPRINTK(fmt, args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) Generic video timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Timings used by the frame buffer interface:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) +----------+---------------------------------------------+----------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) | | ^ | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) | | |upper_margin | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) | | v | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) +----------###############################################----------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) | # ^ # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) | left # | # right | hsync |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) | margin # | xres # margin | len |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) |<-------->#<---------------+--------------------------->#<-------->|<----->|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) | # |yres # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) | # | # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) | # v # | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) +----------###############################################----------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) | | ^ | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) | | |lower_margin | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) | | v | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) +----------+---------------------------------------------+----------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) | | ^ | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) | | |vsync_len | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) | | v | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) +----------+---------------------------------------------+----------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) Amiga video timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) The Amiga native chipsets uses another timing scheme:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) - hsstrt: Start of horizontal synchronization pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) - hsstop: End of horizontal synchronization pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) - htotal: Last value on the line (i.e. line length = htotal + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) - vsstrt: Start of vertical synchronization pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) - vsstop: End of vertical synchronization pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) - vtotal: Last line value (i.e. number of lines = vtotal + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) - hcenter: Start of vertical retrace for interlace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) You can specify the blanking timings independently. Currently I just set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) them equal to the respective synchronization values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) - hbstrt: Start of horizontal blank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) - hbstop: End of horizontal blank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - vbstrt: Start of vertical blank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) - vbstop: End of vertical blank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Horizontal values are in color clock cycles (280 ns), vertical values are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) scanlines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (0, 0) is somewhere in the upper-left corner :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Amiga visible window definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) --------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) Currently I only have values for AGA, SHRES (28 MHz dotclock). Feel free to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) make corrections and/or additions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) Within the above synchronization specifications, the visible window is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) defined by the following parameters (actual register resolutions may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) different; all horizontal values are normalized with respect to the pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clock):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) - diwstrt_h: Horizontal start of the visible window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) - diwstop_h: Horizontal stop + 1(*) of the visible window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) - diwstrt_v: Vertical start of the visible window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) - diwstop_v: Vertical stop of the visible window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) - ddfstrt: Horizontal start of display DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) - ddfstop: Horizontal stop of display DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) - hscroll: Horizontal display output delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) Sprite positioning:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) - sprstrt_h: Horizontal start - 4 of sprite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) - sprstrt_v: Vertical start of sprite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (*) Even Commodore did it wrong in the AGA monitor drivers by not adding 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) Horizontal values are in dotclock cycles (35 ns), vertical values are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) scanlines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) (0, 0) is somewhere in the upper-left corner :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) Dependencies (AGA, SHRES (35 ns dotclock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) -------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) Since there are much more parameters for the Amiga display than for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) frame buffer interface, there must be some dependencies among the Amiga
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) display parameters. Here's what I found out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) - ddfstrt and ddfstop are best aligned to 64 pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) - the chipset needs 64 + 4 horizontal pixels after the DMA start before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) the first pixel is output, so diwstrt_h = ddfstrt + 64 + 4 if you want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) to display the first pixel on the line too. Increase diwstrt_h for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) virtual screen panning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) - the display DMA always fetches 64 pixels at a time (fmode = 3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) - ddfstop is ddfstrt+#pixels - 64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) - diwstop_h = diwstrt_h + xres + 1. Because of the additional 1 this can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) be 1 more than htotal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) - hscroll simply adds a delay to the display output. Smooth horizontal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) panning needs an extra 64 pixels on the left to prefetch the pixels that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) `fall off' on the left.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) - if ddfstrt < 192, the sprite DMA cycles are all stolen by the bitplane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DMA, so it's best to make the DMA start as late as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) - you really don't want to make ddfstrt < 128, since this will steal DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cycles from the other DMA channels (audio, floppy and Chip RAM refresh).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) - I make diwstop_h and diwstop_v as large as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) General dependencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) - all values are SHRES pixel (35ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) table 1:fetchstart table 2:prefetch table 3:fetchsize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ------------------ ---------------- -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) Pixclock # SHRES|HIRES|LORES # SHRES|HIRES|LORES # SHRES|HIRES|LORES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) -------------#------+-----+------#------+-----+------#------+-----+------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) Bus width 1x # 16 | 32 | 64 # 16 | 32 | 64 # 64 | 64 | 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) Bus width 2x # 32 | 64 | 128 # 32 | 64 | 64 # 64 | 64 | 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) Bus width 4x # 64 | 128 | 256 # 64 | 64 | 64 # 64 | 128 | 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) - chipset needs 4 pixels before the first pixel is output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) - ddfstrt must be aligned to fetchstart (table 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) - chipset needs also prefetch (table 2) to get first pixel data, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ddfstrt = ((diwstrt_h - 4) & -fetchstart) - prefetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) - for horizontal panning decrease diwstrt_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) - the length of a fetchline must be aligned to fetchsize (table 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) - if fetchstart is smaller than fetchsize, then ddfstrt can a little bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) moved to optimize use of dma (useful for OCS/ECS overscan displays)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) - ddfstop is ddfstrt + ddfsize - fetchsize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) - If C= didn't change anything for AGA, then at following positions the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dma bus is already used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ddfstrt < 48 -> memory refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) < 96 -> disk dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) < 160 -> audio dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) < 192 -> sprite 0 dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) < 416 -> sprite dma (32 per sprite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) - in accordance with the hardware reference manual a hardware stop is at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 192, but AGA (ECS?) can go below this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DMA priorities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) Since there are limits on the earliest start value for display DMA and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) display of sprites, I use the following policy on horizontal panning and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) the hardware cursor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) - if you want to start display DMA too early, you lose the ability to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) do smooth horizontal panning (xpanstep 1 -> 64).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) - if you want to go even further, you lose the hardware cursor too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IMHO a hardware cursor is more important for X than horizontal scrolling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) so that's my motivation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) Implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ami_decode_var() converts the frame buffer values to the Amiga values. It's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) just a `straightforward' implementation of the above rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) Standard VGA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) xres yres left right upper lower hsync vsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ---- ---- ---- ----- ----- ----- ----- -----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 80x25 720 400 27 45 35 12 108 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 80x30 720 480 27 45 30 9 108 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) These were taken from a XFree86 configuration file, recalculated for a 28 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dotclock (Amigas don't have a 25 MHz dotclock) and converted to frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) generic timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) As a comparison, graphics/monitor.h suggests the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) xres yres left right upper lower hsync vsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ---- ---- ---- ----- ----- ----- ----- -----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) VGA 640 480 52 112 24 19 112 - 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) VGA70 640 400 52 112 27 21 112 - 2 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) Sync polarities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ---------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) VSYNC HSYNC Vertical size Vertical total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ----- ----- ------------- --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) + + Reserved Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) + - 400 414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) - + 350 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) - - 480 496
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) Source: CL-GD542X Technical Reference Manual, Cirrus Logic, Oct 1992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) Broadcast video timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) According to the CCIR and RETMA specifications, we have the following values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CCIR -> PAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) - a scanline is 64 µs long, of which 52.48 µs are visible. This is about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 736 visible 70 ns pixels per line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) - we have 625 scanlines, of which 575 are visible (interlaced); after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rounding this becomes 576.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) RETMA -> NTSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) - a scanline is 63.5 µs long, of which 53.5 µs are visible. This is about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 736 visible 70 ns pixels per line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) - we have 525 scanlines, of which 485 are visible (interlaced); after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) rounding this becomes 484.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) Thus if you want a PAL compatible display, you have to do the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) - set the FB_SYNC_BROADCAST flag to indicate that standard broadcast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) timings are to be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) - make sure upper_margin + yres + lower_margin + vsync_len = 625 for an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) interlaced, 312 for a non-interlaced and 156 for a doublescanned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) - make sure left_margin + xres + right_margin + hsync_len = 1816 for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SHRES, 908 for a HIRES and 454 for a LORES display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) - the left visible part begins at 360 (SHRES; HIRES:180, LORES:90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) left_margin + 2 * hsync_len must be greater or equal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) - the upper visible part begins at 48 (interlaced; non-interlaced:24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) doublescanned:12), upper_margin + 2 * vsync_len must be greater or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) equal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) - ami_encode_var() calculates margins with a hsync of 5320 ns and a vsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) of 4 scanlines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) The settings for a NTSC compatible display are straightforward.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) Note that in a strict sense the PAL and NTSC standards only define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) encoding of the color part (chrominance) of the video signal and don't say
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) anything about horizontal/vertical synchronization nor refresh rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) -- Geert --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Custom Chipset Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CUSTOM_OFS(fld) ((long)&((struct CUSTOM*)0)->fld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * BPLCON0 -- Bitplane Control Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define BPC0_HIRES (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define BPC0_BPU2 (0x4000) /* Bit plane used count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define BPC0_BPU1 (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define BPC0_BPU0 (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define BPC0_HAM (0x0800) /* HAM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define BPC0_DPF (0x0400) /* Double playfield */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define BPC0_COLOR (0x0200) /* Enable colorburst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define BPC0_GAUD (0x0100) /* Genlock audio enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define BPC0_UHRES (0x0080) /* Ultrahi res enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define BPC0_SHRES (0x0040) /* Super hi res mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define BPC0_BYPASS (0x0020) /* Bypass LUT - AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define BPC0_BPU3 (0x0010) /* AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define BPC0_LPEN (0x0008) /* Light pen enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define BPC0_LACE (0x0004) /* Interlace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define BPC0_ERSY (0x0002) /* External resync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define BPC0_ECSENA (0x0001) /* ECS enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * BPLCON2 -- Bitplane Control Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define BPC2_ZDBPSEL2 (0x4000) /* Bitplane to be used for ZD - AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define BPC2_ZDBPSEL1 (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define BPC2_ZDBPSEL0 (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define BPC2_ZDBPEN (0x0800) /* Enable ZD with ZDBPSELx - AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define BPC2_ZDCTEN (0x0400) /* Enable ZD with palette bit #31 - AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define BPC2_KILLEHB (0x0200) /* Kill EHB mode - AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define BPC2_RDRAM (0x0100) /* Color table accesses read, not write - AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define BPC2_SOGEN (0x0080) /* SOG output pin high - AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define BPC2_PF2PRI (0x0040) /* PF2 priority over PF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define BPC2_PF2P2 (0x0020) /* PF2 priority wrt sprites */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define BPC2_PF2P1 (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define BPC2_PF2P0 (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define BPC2_PF1P2 (0x0004) /* ditto PF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define BPC2_PF1P1 (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define BPC2_PF1P0 (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * BPLCON3 -- Bitplane Control Register 3 (AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define BPC3_BANK2 (0x8000) /* Bits to select color register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define BPC3_BANK1 (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define BPC3_BANK0 (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define BPC3_PF2OF2 (0x1000) /* Bits for color table offset when PF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define BPC3_PF2OF1 (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define BPC3_PF2OF0 (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define BPC3_LOCT (0x0200) /* Color register writes go to low bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define BPC3_SPRES1 (0x0080) /* Sprite resolution bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define BPC3_SPRES0 (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BPC3_BRDRBLNK (0x0020) /* Border blanked? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BPC3_BRDRTRAN (0x0010) /* Border transparent? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define BPC3_ZDCLKEN (0x0004) /* ZD pin is 14 MHz (HIRES) clock output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define BPC3_BRDRSPRT (0x0002) /* Sprites in border? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define BPC3_EXTBLKEN (0x0001) /* BLANK programmable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * BPLCON4 -- Bitplane Control Register 4 (AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define BPC4_BPLAM7 (0x8000) /* bitplane color XOR field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define BPC4_BPLAM6 (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define BPC4_BPLAM5 (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define BPC4_BPLAM4 (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define BPC4_BPLAM3 (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define BPC4_BPLAM2 (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define BPC4_BPLAM1 (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define BPC4_BPLAM0 (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define BPC4_ESPRM7 (0x0080) /* 4 high bits for even sprite colors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define BPC4_ESPRM6 (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define BPC4_ESPRM5 (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define BPC4_ESPRM4 (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define BPC4_OSPRM7 (0x0008) /* 4 high bits for odd sprite colors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define BPC4_OSPRM6 (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define BPC4_OSPRM5 (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define BPC4_OSPRM4 (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * BEAMCON0 -- Beam Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define BMC0_HARDDIS (0x4000) /* Disable hardware limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define BMC0_LPENDIS (0x2000) /* Disable light pen latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define BMC0_VARVBEN (0x1000) /* Enable variable vertical blank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define BMC0_LOLDIS (0x0800) /* Disable long/short line toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define BMC0_CSCBEN (0x0400) /* Composite sync/blank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define BMC0_VARVSYEN (0x0200) /* Enable variable vertical sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define BMC0_VARHSYEN (0x0100) /* Enable variable horizontal sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define BMC0_VARBEAMEN (0x0080) /* Enable variable beam counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define BMC0_DUAL (0x0040) /* Enable alternate horizontal beam counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define BMC0_PAL (0x0020) /* Set decodes for PAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define BMC0_VARCSYEN (0x0010) /* Enable variable composite sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define BMC0_BLANKEN (0x0008) /* Blank enable (no longer used on AGA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define BMC0_CSYTRUE (0x0004) /* CSY polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define BMC0_VSYTRUE (0x0002) /* VSY polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define BMC0_HSYTRUE (0x0001) /* HSY polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * FMODE -- Fetch Mode Control Register (AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define FMODE_SSCAN2 (0x8000) /* Sprite scan-doubling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define FMODE_BSCAN2 (0x4000) /* Use PF2 modulus every other line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define FMODE_SPAGEM (0x0008) /* Sprite page mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define FMODE_SPR32 (0x0004) /* Sprite 32 bit fetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define FMODE_BPAGEM (0x0002) /* Bitplane page mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define FMODE_BPL32 (0x0001) /* Bitplane 32 bit fetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Tags used to indicate a specific Pixel Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * clk_shift is the shift value to get the timings in 35 ns units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) enum { TAG_SHRES, TAG_HIRES, TAG_LORES };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Tags used to indicate the specific chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) enum { TAG_OCS, TAG_ECS, TAG_AGA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Tags used to indicate the memory bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) enum { TAG_FMODE_1, TAG_FMODE_2, TAG_FMODE_4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Clock Definitions, Maximum Display Depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * These depend on the E-Clock or the Chipset, so they are filled in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * dynamically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static u_long pixclock[3]; /* SHRES/HIRES/LORES: index = clk_shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static u_short maxdepth[3]; /* SHRES/HIRES/LORES: index = clk_shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static u_short maxfmode, chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Broadcast Video Timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Horizontal values are in 35 ns (SHRES) units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Vertical values are in interlaced scanlines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define PAL_DIWSTRT_H (360) /* PAL Window Limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define PAL_DIWSTRT_V (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define PAL_HTOTAL (1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define PAL_VTOTAL (625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define NTSC_DIWSTRT_H (360) /* NTSC Window Limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define NTSC_DIWSTRT_V (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define NTSC_HTOTAL (1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define NTSC_VTOTAL (525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Various macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define up2(v) (((v) + 1) & -2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define down2(v) ((v) & -2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define div2(v) ((v)>>1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define mod2(v) ((v) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define up4(v) (((v) + 3) & -4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define down4(v) ((v) & -4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define mul4(v) ((v) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define div4(v) ((v)>>2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define mod4(v) ((v) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define up8(v) (((v) + 7) & -8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define down8(v) ((v) & -8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define div8(v) ((v)>>3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define mod8(v) ((v) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define up16(v) (((v) + 15) & -16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define down16(v) ((v) & -16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define div16(v) ((v)>>4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define mod16(v) ((v) & 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define up32(v) (((v) + 31) & -32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define down32(v) ((v) & -32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define div32(v) ((v)>>5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define mod32(v) ((v) & 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define up64(v) (((v) + 63) & -64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define down64(v) ((v) & -64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define div64(v) ((v)>>6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define mod64(v) ((v) & 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define upx(x, v) (((v) + (x) - 1) & -(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define downx(x, v) ((v) & -(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define modx(x, v) ((v) & ((x) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * FIXME: Use C variants of the code marked with #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * in the driver. It shouldn't negatively affect the performance and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * is required for APUS support (once it is re-added to the kernel).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Needs to be tested on the hardware though..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* if x1 is not a constant, this macro won't make real sense :-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define DIVUL(x1, x2) ({int res; asm("divul %1,%2,%3": "=d" (res): \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "d" (x2), "d" ((long)((x1) / 0x100000000ULL)), "0" ((long)(x1))); res;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* We know a bit about the numbers, so we can do it this way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define DIVUL(x1, x2) ((((long)((unsigned long long)x1 >> 8) / x2) << 8) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ((((long)((unsigned long long)x1 >> 8) % x2) << 8) / x2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define highw(x) ((u_long)(x)>>16 & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define loww(x) ((u_long)(x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define custom amiga_custom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define VBlankOn() custom.intena = IF_SETCLR|IF_COPER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define VBlankOff() custom.intena = IF_COPER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * Chip RAM we reserve for the Frame Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * This defines the Maximum Virtual Screen Size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * (Setable per kernel options?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define VIDEOMEMSIZE_AGA_2M (1310720) /* AGA (2MB) : max 1280*1024*256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define VIDEOMEMSIZE_AGA_1M (786432) /* AGA (1MB) : max 1024*768*256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define VIDEOMEMSIZE_ECS_2M (655360) /* ECS (2MB) : max 1280*1024*16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define VIDEOMEMSIZE_ECS_1M (393216) /* ECS (1MB) : max 1024*768*16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define VIDEOMEMSIZE_OCS (262144) /* OCS : max ca. 800*600*16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SPRITEMEMSIZE (64 * 64 / 4) /* max 64*64*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define DUMMYSPRITEMEMSIZE (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static u_long spritememory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define CHIPRAM_SAFETY_LIMIT (16384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static u_long videomemory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * This is the earliest allowed start of fetching display data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * Only if you really want no hardware cursor and audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * set this to 128, but let it better at 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static u_long min_fstrt = 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define assignchunk(name, type, ptr, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (name) = (type)(ptr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ptr += size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Copper Instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define CMOVE(val, reg) (CUSTOM_OFS(reg) << 16 | (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define CMOVE2(val, reg) ((CUSTOM_OFS(reg) + 2) << 16 | (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define CWAIT(x, y) (((y) & 0x1fe) << 23 | ((x) & 0x7f0) << 13 | 0x0001fffe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define CEND (0xfffffffe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u_long l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u_short w[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) } copins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static struct copdisplay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) copins *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) copins *wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) copins *list[2][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) copins *rebuild[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } copdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static u_short currentcop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * Hardware Cursor API Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * These used to be in linux/fb.h, but were preliminary and used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * amifb only anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define FBIOGET_FCURSORINFO 0x4607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define FBIOGET_VCURSORINFO 0x4608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define FBIOPUT_VCURSORINFO 0x4609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define FBIOGET_CURSORSTATE 0x460A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define FBIOPUT_CURSORSTATE 0x460B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct fb_fix_cursorinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) __u16 crsr_width; /* width and height of the cursor in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) __u16 crsr_height; /* pixels (zero if no cursor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) __u16 crsr_xsize; /* cursor size in display pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) __u16 crsr_ysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) __u16 crsr_color1; /* colormap entry for cursor color1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) __u16 crsr_color2; /* colormap entry for cursor color2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct fb_var_cursorinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) __u16 xspot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __u16 yspot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __u8 data[1]; /* field with [height][width] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct fb_cursorstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __s16 xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) __s16 yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define FB_CURSOR_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define FB_CURSOR_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define FB_CURSOR_FLASH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Hardware Cursor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int cursorrate = 20; /* Number of frames/flash toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static u_short cursorstate = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static u_short cursormode = FB_CURSOR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static u_short *lofsprite, *shfsprite, *dummysprite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Current Video Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct amifb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* General Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int xres; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int yres; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int vxres; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int vyres; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int xoffset; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int yoffset; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u_short bpp; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u_short clk_shift; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u_short line_shift; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int vmode; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u_short diwstrt_h; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u_short diwstop_h; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u_short diwstrt_v; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u_short diwstop_v; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u_long next_line; /* modulo for next line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u_long next_plane; /* modulo for next plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Cursor Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) short crsr_x; /* movecursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) short crsr_y; /* movecursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) short spot_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) short spot_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u_short height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u_short width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u_short fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) } crsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* OCS Hardware Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u_long bplpt0; /* vmode, pan (Note: physical address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u_long bplpt0wrap; /* vmode, pan (Note: physical address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u_short ddfstrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u_short ddfstop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u_short bpl1mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u_short bpl2mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u_short bplcon0; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u_short bplcon1; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u_short htotal; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u_short vtotal; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Additional ECS Hardware Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u_short bplcon3; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u_short beamcon0; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u_short hsstrt; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u_short hsstop; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u_short hbstrt; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u_short hbstop; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u_short vsstrt; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u_short vsstop; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u_short vbstrt; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u_short vbstop; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u_short hcenter; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Additional AGA Hardware Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u_short fmode; /* vmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * Saved color entry 0 so we can restore it when unblanking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static u_char red0, green0, blue0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #if defined(CONFIG_FB_AMIGA_ECS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static u_short ecs_palette[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * Latches for Display Changes during VBlank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static u_short do_vmode_full = 0; /* Change the Video Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static u_short do_vmode_pan = 0; /* Update the Video Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static short do_blank = 0; /* (Un)Blank the Screen (±1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static u_short do_cursor = 0; /* Move the Cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * Various Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static u_short is_blanked = 0; /* Screen is Blanked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static u_short is_lace = 0; /* Screen is laced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Predefined Video Modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static struct fb_videomode ami_modedb[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * AmigaOS Video Modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * If you change these, make sure to update DEFMODE_* as well!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* 640x200, 15 kHz, 60 Hz (NTSC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "ntsc", 60, 640, 200, TAG_HIRES, 106, 86, 44, 16, 76, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* 640x400, 15 kHz, 60 Hz interlaced (NTSC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "ntsc-lace", 60, 640, 400, TAG_HIRES, 106, 86, 88, 33, 76, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* 640x256, 15 kHz, 50 Hz (PAL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "pal", 50, 640, 256, TAG_HIRES, 106, 86, 40, 14, 76, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* 640x512, 15 kHz, 50 Hz interlaced (PAL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "pal-lace", 50, 640, 512, TAG_HIRES, 106, 86, 80, 29, 76, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* 640x480, 29 kHz, 57 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "multiscan", 57, 640, 480, TAG_SHRES, 96, 112, 29, 8, 72, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* 640x960, 29 kHz, 57 Hz interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "multiscan-lace", 57, 640, 960, TAG_SHRES, 96, 112, 58, 16, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* 640x200, 15 kHz, 72 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "euro36", 72, 640, 200, TAG_HIRES, 92, 124, 6, 6, 52, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* 640x400, 15 kHz, 72 Hz interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "euro36-lace", 72, 640, 400, TAG_HIRES, 92, 124, 12, 12, 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* 640x400, 29 kHz, 68 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "euro72", 68, 640, 400, TAG_SHRES, 164, 92, 9, 9, 80, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* 640x800, 29 kHz, 68 Hz interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) "euro72-lace", 68, 640, 800, TAG_SHRES, 164, 92, 18, 18, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* 800x300, 23 kHz, 70 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "super72", 70, 800, 300, TAG_SHRES, 212, 140, 10, 11, 80, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* 800x600, 23 kHz, 70 Hz interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "super72-lace", 70, 800, 600, TAG_SHRES, 212, 140, 20, 22, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* 640x200, 27 kHz, 57 Hz doublescan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "dblntsc", 57, 640, 200, TAG_SHRES, 196, 124, 18, 17, 80, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) 0, FB_VMODE_DOUBLE | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* 640x400, 27 kHz, 57 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "dblntsc-ff", 57, 640, 400, TAG_SHRES, 196, 124, 36, 35, 80, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* 640x800, 27 kHz, 57 Hz interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) "dblntsc-lace", 57, 640, 800, TAG_SHRES, 196, 124, 72, 70, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* 640x256, 27 kHz, 47 Hz doublescan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "dblpal", 47, 640, 256, TAG_SHRES, 196, 124, 14, 13, 80, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) 0, FB_VMODE_DOUBLE | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* 640x512, 27 kHz, 47 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "dblpal-ff", 47, 640, 512, TAG_SHRES, 196, 124, 28, 27, 80, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* 640x1024, 27 kHz, 47 Hz interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "dblpal-lace", 47, 640, 1024, TAG_SHRES, 196, 124, 56, 54, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) 0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * VGA Video Modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* 640x480, 31 kHz, 60 Hz (VGA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) "vga", 60, 640, 480, TAG_SHRES, 64, 96, 30, 9, 112, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* 640x400, 31 kHz, 70 Hz (VGA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "vga70", 70, 640, 400, TAG_SHRES, 64, 96, 35, 12, 112, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) FB_SYNC_VERT_HIGH_ACT | FB_SYNC_COMP_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * A2024 video modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * These modes don't work yet because there's no A2024 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* 1024x800, 10 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "a2024-10", 10, 1024, 800, TAG_HIRES, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* 1024x800, 15 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) "a2024-15", 15, 1024, 800, TAG_HIRES, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) 0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define NUM_TOTAL_MODES ARRAY_SIZE(ami_modedb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static char *mode_option __initdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int round_down_bpp = 1; /* for mode probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * Some default modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define DEFMODE_PAL 2 /* "pal" for PAL OCS/ECS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define DEFMODE_NTSC 0 /* "ntsc" for NTSC OCS/ECS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define DEFMODE_AMBER_PAL 3 /* "pal-lace" for flicker fixed PAL (A3000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define DEFMODE_AMBER_NTSC 1 /* "ntsc-lace" for flicker fixed NTSC (A3000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define DEFMODE_AGA 19 /* "vga70" for AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int amifb_ilbm = 0; /* interleaved or normal bitplanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static u32 amifb_hfmin __initdata; /* monitor hfreq lower limit (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static u32 amifb_hfmax __initdata; /* monitor hfreq upper limit (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static u16 amifb_vfmin __initdata; /* monitor vfreq lower limit (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static u16 amifb_vfmax __initdata; /* monitor vfreq upper limit (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Macros for the conversion from real world values to hardware register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * This helps us to keep our attention on the real stuff...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * Hardware limits for AGA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * parameter min max step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * --------- --- ---- ----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * diwstrt_h 0 2047 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * diwstrt_v 0 2047 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * diwstop_h 0 4095 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * diwstop_v 0 4095 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * ddfstrt 0 2032 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * ddfstop 0 2032 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * htotal 8 2048 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * hsstrt 0 2040 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * hsstop 0 2040 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * vtotal 1 4096 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * vsstrt 0 4095 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * vsstop 0 4095 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * hcenter 0 2040 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * hbstrt 0 2047 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * hbstop 0 2047 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * vbstrt 0 4095 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * vbstop 0 4095 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * Horizontal values are in 35 ns (SHRES) pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * Vertical values are in half scanlines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* bplcon1 (smooth scrolling) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define hscroll2hw(hscroll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) (((hscroll) << 12 & 0x3000) | ((hscroll) << 8 & 0xc300) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ((hscroll) << 4 & 0x0c00) | ((hscroll) << 2 & 0x00f0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ((hscroll)>>2 & 0x000f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* diwstrt/diwstop/diwhigh (visible display window) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define diwstrt2hw(diwstrt_h, diwstrt_v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) (((diwstrt_v) << 7 & 0xff00) | ((diwstrt_h)>>2 & 0x00ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define diwstop2hw(diwstop_h, diwstop_v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) (((diwstop_v) << 7 & 0xff00) | ((diwstop_h)>>2 & 0x00ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define diwhigh2hw(diwstrt_h, diwstrt_v, diwstop_h, diwstop_v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) (((diwstop_h) << 3 & 0x2000) | ((diwstop_h) << 11 & 0x1800) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ((diwstop_v)>>1 & 0x0700) | ((diwstrt_h)>>5 & 0x0020) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ((diwstrt_h) << 3 & 0x0018) | ((diwstrt_v)>>9 & 0x0007))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* ddfstrt/ddfstop (display DMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define ddfstrt2hw(ddfstrt) div8(ddfstrt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define ddfstop2hw(ddfstop) div8(ddfstop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* hsstrt/hsstop/htotal/vsstrt/vsstop/vtotal/hcenter (sync timings) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define hsstrt2hw(hsstrt) (div8(hsstrt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define hsstop2hw(hsstop) (div8(hsstop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define htotal2hw(htotal) (div8(htotal) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define vsstrt2hw(vsstrt) (div2(vsstrt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define vsstop2hw(vsstop) (div2(vsstop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define vtotal2hw(vtotal) (div2(vtotal) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define hcenter2hw(htotal) (div8(htotal))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* hbstrt/hbstop/vbstrt/vbstop (blanking timings) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define hbstrt2hw(hbstrt) (((hbstrt) << 8 & 0x0700) | ((hbstrt)>>3 & 0x00ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define hbstop2hw(hbstop) (((hbstop) << 8 & 0x0700) | ((hbstop)>>3 & 0x00ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define vbstrt2hw(vbstrt) (div2(vbstrt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define vbstop2hw(vbstop) (div2(vbstop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* colour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define rgb2hw8_high(red, green, blue) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) (((red & 0xf0) << 4) | (green & 0xf0) | ((blue & 0xf0)>>4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define rgb2hw8_low(red, green, blue) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) (((red & 0x0f) << 8) | ((green & 0x0f) << 4) | (blue & 0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define rgb2hw4(red, green, blue) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) (((red & 0xf0) << 4) | (green & 0xf0) | ((blue & 0xf0)>>4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define rgb2hw2(red, green, blue) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) (((red & 0xc0) << 4) | (green & 0xc0) | ((blue & 0xc0)>>4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* sprpos/sprctl (sprite positioning) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define spr2hw_pos(start_v, start_h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) (((start_v) << 7 & 0xff00) | ((start_h)>>3 & 0x00ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define spr2hw_ctl(start_v, start_h, stop_v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) (((stop_v) << 7 & 0xff00) | ((start_v)>>4 & 0x0040) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ((stop_v)>>5 & 0x0020) | ((start_h) << 3 & 0x0018) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ((start_v)>>7 & 0x0004) | ((stop_v)>>8 & 0x0002) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ((start_h)>>2 & 0x0001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* get current vertical position of beam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define get_vbpos() ((u_short)((*(u_long volatile *)&custom.vposr >> 7) & 0xffe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Copper Initialisation List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define COPINITSIZE (sizeof(copins) * 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) cip_bplcon0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * Long Frame/Short Frame Copper List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * Don't change the order, build_copper()/rebuild_copper() rely on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define COPLISTSIZE (sizeof(copins) * 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) cop_wait, cop_bplcon0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) cop_spr0ptrh, cop_spr0ptrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) cop_diwstrt, cop_diwstop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) cop_diwhigh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * Pixel modes for Bitplanes and Sprites
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static u_short bplpixmode[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) BPC0_SHRES, /* 35 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) BPC0_HIRES, /* 70 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) 0 /* 140 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static u_short sprpixmode[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) BPC3_SPRES1 | BPC3_SPRES0, /* 35 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) BPC3_SPRES1, /* 70 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) BPC3_SPRES0 /* 140 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * Fetch modes for Bitplanes and Sprites
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static u_short bplfetchmode[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) 0, /* 1x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) FMODE_BPL32, /* 2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) FMODE_BPAGEM | FMODE_BPL32 /* 4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static u_short sprfetchmode[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) 0, /* 1x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) FMODE_SPR32, /* 2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) FMODE_SPAGEM | FMODE_SPR32 /* 4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* --------------------------- Hardware routines --------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * Get the video params out of `var'. If a value doesn't fit, round
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * it up, if it's too big, return -EINVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static int ami_decode_var(struct fb_var_screeninfo *var, struct amifb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) const struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) u_short clk_shift, line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u_long maxfetchstop, fstrt, fsize, fconst, xres_n, yres_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) u_int htotal, vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * Find a matching Pixel Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) for (clk_shift = TAG_SHRES; clk_shift <= TAG_LORES; clk_shift++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (var->pixclock <= pixclock[clk_shift])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (clk_shift > TAG_LORES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) DPRINTK("pixclock too high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) par->clk_shift = clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * Check the Geometry Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if ((par->xres = var->xres) < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) par->xres = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if ((par->yres = var->yres) < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) par->yres = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if ((par->vxres = var->xres_virtual) < par->xres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) par->vxres = par->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if ((par->vyres = var->yres_virtual) < par->yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) par->vyres = par->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) par->bpp = var->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (!var->nonstd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (par->bpp < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) par->bpp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (par->bpp > maxdepth[clk_shift]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (round_down_bpp && maxdepth[clk_shift])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) par->bpp = maxdepth[clk_shift];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) DPRINTK("invalid bpp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) } else if (var->nonstd == FB_NONSTD_HAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (par->bpp < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) par->bpp = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (par->bpp != 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (par->bpp < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) par->bpp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (par->bpp != 8 || !IS_AGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) DPRINTK("invalid bpp for ham mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) DPRINTK("unknown nonstd mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * FB_VMODE_SMOOTH_XPAN will be cleared, if one of the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * checks failed and smooth scrolling is not possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) par->vmode = var->vmode | FB_VMODE_SMOOTH_XPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) switch (par->vmode & FB_VMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) case FB_VMODE_INTERLACED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) line_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) case FB_VMODE_NONINTERLACED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) line_shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case FB_VMODE_DOUBLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!IS_AGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) DPRINTK("double mode only possible with aga\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) line_shift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) DPRINTK("unknown video mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) par->line_shift = line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * Vertical and Horizontal Timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) xres_n = par->xres << clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) yres_n = par->yres << line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) par->htotal = down8((var->left_margin + par->xres + var->right_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) var->hsync_len) << clk_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) par->vtotal =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) down2(((var->upper_margin + par->yres + var->lower_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) var->vsync_len) << line_shift) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (IS_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) par->bplcon3 = sprpixmode[clk_shift];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) par->bplcon3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (var->sync & FB_SYNC_BROADCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) par->diwstop_h = par->htotal -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ((var->right_margin - var->hsync_len) << clk_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (IS_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) par->diwstop_h += mod4(var->hsync_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) par->diwstop_h = down4(par->diwstop_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) par->diwstrt_h = par->diwstop_h - xres_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) par->diwstop_v = par->vtotal -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ((var->lower_margin - var->vsync_len) << line_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) par->diwstrt_v = par->diwstop_v - yres_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (par->diwstop_h >= par->htotal + 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) DPRINTK("invalid diwstop_h\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (par->diwstop_v > par->vtotal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) DPRINTK("invalid diwstop_v\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* Initialize sync with some reasonable values for pwrsave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) par->hsstrt = 160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) par->hsstop = 320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) par->vsstrt = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) par->vsstop = 34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) par->hsstrt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) par->hsstop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) par->vsstrt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) par->vsstop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (par->vtotal > (PAL_VTOTAL + NTSC_VTOTAL) / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* PAL video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (par->htotal != PAL_HTOTAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) DPRINTK("htotal invalid for pal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (par->diwstrt_h < PAL_DIWSTRT_H) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) DPRINTK("diwstrt_h too low for pal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (par->diwstrt_v < PAL_DIWSTRT_V) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) DPRINTK("diwstrt_v too low for pal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) htotal = PAL_HTOTAL>>clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) vtotal = PAL_VTOTAL>>1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) par->beamcon0 = BMC0_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) par->bplcon3 |= BPC3_BRDRBLNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) } else if (AMIGAHW_PRESENT(AGNUS_HR_PAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) AMIGAHW_PRESENT(AGNUS_HR_NTSC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) par->beamcon0 = BMC0_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) par->hsstop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) } else if (amiga_vblank != 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) DPRINTK("pal not supported by this chipset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* NTSC video mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * In the AGA chipset seems to be hardware bug with BPC3_BRDRBLNK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * and NTSC activated, so than better let diwstop_h <= 1812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (par->htotal != NTSC_HTOTAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) DPRINTK("htotal invalid for ntsc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (par->diwstrt_h < NTSC_DIWSTRT_H) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) DPRINTK("diwstrt_h too low for ntsc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (par->diwstrt_v < NTSC_DIWSTRT_V) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) DPRINTK("diwstrt_v too low for ntsc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) htotal = NTSC_HTOTAL>>clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) vtotal = NTSC_VTOTAL>>1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) par->beamcon0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) par->bplcon3 |= BPC3_BRDRBLNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) } else if (AMIGAHW_PRESENT(AGNUS_HR_PAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) AMIGAHW_PRESENT(AGNUS_HR_NTSC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) par->beamcon0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) par->hsstop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) } else if (amiga_vblank != 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) DPRINTK("ntsc not supported by this chipset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (par->diwstrt_h >= 1024 || par->diwstop_h < 1024 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) par->diwstrt_v >= 512 || par->diwstop_v < 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) DPRINTK("invalid position for display on ocs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) } else if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* Programmable video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) par->hsstrt = var->right_margin << clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) par->hsstop = (var->right_margin + var->hsync_len) << clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) par->diwstop_h = par->htotal - mod8(par->hsstrt) + 8 - (1 << clk_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (!IS_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) par->diwstop_h = down4(par->diwstop_h) - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) par->diwstrt_h = par->diwstop_h - xres_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) par->hbstop = par->diwstrt_h + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) par->hbstrt = par->diwstop_h + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (par->hbstrt >= par->htotal + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) par->hbstrt -= par->htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) par->hcenter = par->hsstrt + (par->htotal >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) par->vsstrt = var->lower_margin << line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) par->vsstop = (var->lower_margin + var->vsync_len) << line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) par->diwstop_v = par->vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if ((par->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) par->diwstop_v -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) par->diwstrt_v = par->diwstop_v - yres_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) par->vbstop = par->diwstrt_v - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) par->vbstrt = par->diwstop_v - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (par->vtotal > 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) DPRINTK("vtotal too high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (par->htotal > 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) DPRINTK("htotal too high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) par->bplcon3 |= BPC3_EXTBLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) par->beamcon0 = BMC0_HARDDIS | BMC0_VARVBEN | BMC0_LOLDIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) BMC0_VARVSYEN | BMC0_VARHSYEN | BMC0_VARBEAMEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) BMC0_PAL | BMC0_VARCSYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (var->sync & FB_SYNC_HOR_HIGH_ACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) par->beamcon0 |= BMC0_HSYTRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (var->sync & FB_SYNC_VERT_HIGH_ACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) par->beamcon0 |= BMC0_VSYTRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (var->sync & FB_SYNC_COMP_HIGH_ACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) par->beamcon0 |= BMC0_CSYTRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) htotal = par->htotal>>clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) vtotal = par->vtotal>>1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) DPRINTK("only broadcast modes possible for ocs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * Checking the DMA timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) fconst = 16 << maxfmode << clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * smallest window start value without turn off other dma cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * than sprite1-7, unless you change min_fstrt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) fsize = ((maxfmode + clk_shift <= 1) ? fconst : 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) fstrt = downx(fconst, par->diwstrt_h - 4) - fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (fstrt < min_fstrt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) DPRINTK("fetch start too low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * smallest window start value where smooth scrolling is possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) fstrt = downx(fconst, par->diwstrt_h - fconst + (1 << clk_shift) - 4) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (fstrt < min_fstrt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) par->vmode &= ~FB_VMODE_SMOOTH_XPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) maxfetchstop = down16(par->htotal - 80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) fstrt = downx(fconst, par->diwstrt_h - 4) - 64 - fconst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) fsize = upx(fconst, xres_n +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) modx(fconst, downx(1 << clk_shift, par->diwstrt_h - 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (fstrt + fsize > maxfetchstop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) par->vmode &= ~FB_VMODE_SMOOTH_XPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) fsize = upx(fconst, xres_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (fstrt + fsize > maxfetchstop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) DPRINTK("fetch stop too high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (maxfmode + clk_shift <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) fsize = up64(xres_n + fconst - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (min_fstrt + fsize - 64 > maxfetchstop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) par->vmode &= ~FB_VMODE_SMOOTH_XPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) fsize = up64(xres_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (min_fstrt + fsize - 64 > maxfetchstop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) DPRINTK("fetch size too high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) fsize -= 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) fsize -= fconst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * Check if there is enough time to update the bitplane pointers for ywrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (par->htotal - fsize - 64 < par->bpp * 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) par->vmode &= ~FB_VMODE_YWRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * Bitplane calculations and check the Memory Requirements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (amifb_ilbm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) par->next_plane = div8(upx(16 << maxfmode, par->vxres));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) par->next_line = par->bpp * par->next_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (par->next_line * par->vyres > info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) DPRINTK("too few video mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) par->next_line = div8(upx(16 << maxfmode, par->vxres));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) par->next_plane = par->vyres * par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (par->next_plane * par->bpp > info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) DPRINTK("too few video mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * Hardware Register Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) par->bplcon0 = BPC0_COLOR | bplpixmode[clk_shift];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (!IS_OCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) par->bplcon0 |= BPC0_ECSENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (par->bpp == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) par->bplcon0 |= BPC0_BPU3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) par->bplcon0 |= par->bpp << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (var->nonstd == FB_NONSTD_HAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) par->bplcon0 |= BPC0_HAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (var->sync & FB_SYNC_EXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) par->bplcon0 |= BPC0_ERSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (IS_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) par->fmode = bplfetchmode[maxfmode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) switch (par->vmode & FB_VMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) case FB_VMODE_INTERLACED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) par->bplcon0 |= BPC0_LACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) case FB_VMODE_DOUBLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (IS_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) par->fmode |= FMODE_SSCAN2 | FMODE_BSCAN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (!((par->vmode ^ var->vmode) & FB_VMODE_YWRAP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) par->xoffset = var->xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) par->yoffset = var->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (par->vmode & FB_VMODE_YWRAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (par->yoffset >= par->vyres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) par->xoffset = par->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (par->xoffset > upx(16 << maxfmode, par->vxres - par->xres) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) par->yoffset > par->vyres - par->yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) par->xoffset = par->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) par->xoffset = par->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) par->crsr.crsr_x = par->crsr.crsr_y = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) par->crsr.spot_x = par->crsr.spot_y = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) par->crsr.height = par->crsr.width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * Fill the `var' structure based on the values in `par' and maybe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * other values read out of the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static void ami_encode_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) u_short clk_shift, line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) memset(var, 0, sizeof(struct fb_var_screeninfo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) clk_shift = par->clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) line_shift = par->line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) var->xres = par->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) var->yres = par->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) var->xres_virtual = par->vxres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) var->yres_virtual = par->vyres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) var->xoffset = par->xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) var->yoffset = par->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) var->bits_per_pixel = par->bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) var->grayscale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) var->red.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) var->red.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) var->red.length = par->bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (par->bplcon0 & BPC0_HAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) var->red.length -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) var->blue = var->green = var->red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) var->transp.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) var->transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) var->transp.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (par->bplcon0 & BPC0_HAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) var->nonstd = FB_NONSTD_HAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) var->nonstd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) var->activate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) var->height = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) var->width = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) var->pixclock = pixclock[clk_shift];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (IS_AGA && par->fmode & FMODE_BSCAN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) var->vmode = FB_VMODE_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) else if (par->bplcon0 & BPC0_LACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) var->vmode = FB_VMODE_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) var->vmode = FB_VMODE_NONINTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (!IS_OCS && par->beamcon0 & BMC0_VARBEAMEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) var->hsync_len = (par->hsstop - par->hsstrt)>>clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) var->right_margin = par->hsstrt>>clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) var->left_margin = (par->htotal>>clk_shift) - var->xres - var->right_margin - var->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) var->vsync_len = (par->vsstop - par->vsstrt)>>line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) var->lower_margin = par->vsstrt>>line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) var->upper_margin = (par->vtotal>>line_shift) - var->yres - var->lower_margin - var->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) var->sync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (par->beamcon0 & BMC0_HSYTRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) var->sync |= FB_SYNC_HOR_HIGH_ACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (par->beamcon0 & BMC0_VSYTRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) var->sync |= FB_SYNC_VERT_HIGH_ACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (par->beamcon0 & BMC0_CSYTRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) var->sync |= FB_SYNC_COMP_HIGH_ACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) var->sync = FB_SYNC_BROADCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) var->hsync_len = (152>>clk_shift) + mod4(par->diwstop_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) var->right_margin = ((par->htotal - down4(par->diwstop_h))>>clk_shift) + var->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) var->left_margin = (par->htotal>>clk_shift) - var->xres - var->right_margin - var->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) var->vsync_len = 4>>line_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) var->lower_margin = ((par->vtotal - par->diwstop_v)>>line_shift) + var->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) var->upper_margin = (((par->vtotal - 2)>>line_shift) + 1) - var->yres -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) var->lower_margin - var->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (par->bplcon0 & BPC0_ERSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) var->sync |= FB_SYNC_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (par->vmode & FB_VMODE_YWRAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) var->vmode |= FB_VMODE_YWRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) * Update hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static void ami_update_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct amifb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) short clk_shift, vshift, fstrt, fsize, fstop, fconst, shift, move, mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) clk_shift = par->clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (!(par->vmode & FB_VMODE_SMOOTH_XPAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) par->xoffset = upx(16 << maxfmode, par->xoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) fconst = 16 << maxfmode << clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) vshift = modx(16 << maxfmode, par->xoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) fstrt = par->diwstrt_h - (vshift << clk_shift) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) fsize = (par->xres + vshift) << clk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) shift = modx(fconst, fstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) move = downx(2 << maxfmode, div8(par->xoffset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (maxfmode + clk_shift > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) fstrt = downx(fconst, fstrt) - 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) fsize = upx(fconst, fsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) fstop = fstrt + fsize - fconst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) mod = fstrt = downx(fconst, fstrt) - fconst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) fstop = fstrt + upx(fconst, fsize) - 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) fsize = up64(fsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) fstrt = fstop - fsize + 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (fstrt < min_fstrt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) fstop += min_fstrt - fstrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) fstrt = min_fstrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) move = move - div8((mod - fstrt)>>clk_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) mod = par->next_line - div8(fsize>>clk_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) par->ddfstrt = fstrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) par->ddfstop = fstop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) par->bplcon1 = hscroll2hw(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) par->bpl2mod = mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (par->bplcon0 & BPC0_LACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) par->bpl2mod += par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (IS_AGA && (par->fmode & FMODE_BSCAN2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) par->bpl1mod = -div8(fsize>>clk_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) par->bpl1mod = par->bpl2mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (par->yoffset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) par->bplpt0 = info->fix.smem_start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) par->next_line * par->yoffset + move;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (par->vmode & FB_VMODE_YWRAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (par->yoffset > par->vyres - par->yres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) par->bplpt0wrap = info->fix.smem_start + move;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (par->bplcon0 & BPC0_LACE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) mod2(par->diwstrt_v + par->vyres -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) par->yoffset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) par->bplpt0wrap += par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) par->bplpt0 = info->fix.smem_start + move;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (par->bplcon0 & BPC0_LACE && mod2(par->diwstrt_v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) par->bplpt0 += par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * Pan or Wrap the Display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * in `var'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static void ami_pan_var(struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) struct amifb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) par->xoffset = var->xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) par->yoffset = var->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (var->vmode & FB_VMODE_YWRAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) par->vmode |= FB_VMODE_YWRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) par->vmode &= ~FB_VMODE_YWRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) do_vmode_pan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ami_update_par(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) do_vmode_pan = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static void ami_update_display(const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) custom.bplcon1 = par->bplcon1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) custom.bpl1mod = par->bpl1mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) custom.bpl2mod = par->bpl2mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) custom.ddfstrt = ddfstrt2hw(par->ddfstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) custom.ddfstop = ddfstop2hw(par->ddfstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * Change the video mode (called by VBlank interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static void ami_init_display(const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) custom.bplcon0 = par->bplcon0 & ~BPC0_LACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) custom.bplcon2 = (IS_OCS ? 0 : BPC2_KILLEHB) | BPC2_PF2P2 | BPC2_PF1P2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) custom.bplcon3 = par->bplcon3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (IS_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) custom.bplcon4 = BPC4_ESPRM4 | BPC4_OSPRM4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (par->beamcon0 & BMC0_VARBEAMEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) custom.htotal = htotal2hw(par->htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) custom.hbstrt = hbstrt2hw(par->hbstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) custom.hbstop = hbstop2hw(par->hbstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) custom.hsstrt = hsstrt2hw(par->hsstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) custom.hsstop = hsstop2hw(par->hsstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) custom.hcenter = hcenter2hw(par->hcenter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) custom.vtotal = vtotal2hw(par->vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) custom.vbstrt = vbstrt2hw(par->vbstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) custom.vbstop = vbstop2hw(par->vbstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) custom.vsstrt = vsstrt2hw(par->vsstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) custom.vsstop = vsstop2hw(par->vsstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (!IS_OCS || par->hsstop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) custom.beamcon0 = par->beamcon0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (IS_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) custom.fmode = par->fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * The minimum period for audio depends on htotal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) amiga_audio_min_period = div16(par->htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) is_lace = par->bplcon0 & BPC0_LACE ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (is_lace) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) i = custom.vposr >> 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) custom.vposw = custom.vposr | 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) custom.vposw = custom.vposr | 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) custom.cop2lc = (u_short *)ZTWO_PADDR(copdisplay.list[currentcop][i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * (Un)Blank the screen (called by VBlank interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static void ami_do_blank(const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #if defined(CONFIG_FB_AMIGA_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) u_short bplcon3 = par->bplcon3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) u_char red, green, blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (do_blank > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) custom.dmacon = DMAF_RASTER | DMAF_SPRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) red = green = blue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (!IS_OCS && do_blank > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) switch (do_blank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) case FB_BLANK_VSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) custom.hsstrt = hsstrt2hw(par->hsstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) custom.hsstop = hsstop2hw(par->hsstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) custom.vsstrt = vsstrt2hw(par->vtotal + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) custom.vsstop = vsstop2hw(par->vtotal + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case FB_BLANK_HSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) custom.hsstrt = hsstrt2hw(par->htotal + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) custom.hsstop = hsstop2hw(par->htotal + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) custom.vsstrt = vsstrt2hw(par->vsstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) custom.vsstop = vsstrt2hw(par->vsstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) case FB_BLANK_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) custom.hsstrt = hsstrt2hw(par->htotal + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) custom.hsstop = hsstop2hw(par->htotal + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) custom.vsstrt = vsstrt2hw(par->vtotal + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) custom.vsstop = vsstop2hw(par->vtotal + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (!(par->beamcon0 & BMC0_VARBEAMEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) custom.htotal = htotal2hw(par->htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) custom.vtotal = vtotal2hw(par->vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) custom.beamcon0 = BMC0_HARDDIS | BMC0_VARBEAMEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) BMC0_VARVSYEN | BMC0_VARHSYEN | BMC0_VARCSYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) custom.dmacon = DMAF_SETCLR | DMAF_RASTER | DMAF_SPRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) red = red0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) green = green0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) blue = blue0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) custom.hsstrt = hsstrt2hw(par->hsstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) custom.hsstop = hsstop2hw(par->hsstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) custom.vsstrt = vsstrt2hw(par->vsstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) custom.vsstop = vsstop2hw(par->vsstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) custom.beamcon0 = par->beamcon0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #if defined(CONFIG_FB_AMIGA_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (IS_AGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) custom.bplcon3 = bplcon3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) custom.color[0] = rgb2hw8_high(red, green, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) custom.bplcon3 = bplcon3 | BPC3_LOCT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) custom.color[0] = rgb2hw8_low(red, green, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) custom.bplcon3 = bplcon3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #if defined(CONFIG_FB_AMIGA_ECS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (par->bplcon0 & BPC0_SHRES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) u_short color, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) mask = 0x3333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) color = rgb2hw2(red, green, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) for (i = 12; i >= 0; i -= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) mask <<= 2; color >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) for (i = 3; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) custom.color[0] = rgb2hw4(red, green, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) is_blanked = do_blank > 0 ? do_blank : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static int ami_get_fix_cursorinfo(struct fb_fix_cursorinfo *fix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) fix->crsr_width = fix->crsr_xsize = par->crsr.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) fix->crsr_height = fix->crsr_ysize = par->crsr.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) fix->crsr_color1 = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) fix->crsr_color2 = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static int ami_get_var_cursorinfo(struct fb_var_cursorinfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) u_char __user *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) register u_short *lspr, *sspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) register u_long datawords asm ("d2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) register u_long datawords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) register short delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) register u_char color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) short height, width, bits, words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) int size, alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) size = par->crsr.height * par->crsr.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) alloc = var->height * var->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) var->height = par->crsr.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) var->width = par->crsr.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) var->xspot = par->crsr.spot_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) var->yspot = par->crsr.spot_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (size > var->height * var->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return -ENAMETOOLONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) delta = 1 << par->crsr.fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) lspr = lofsprite + (delta << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (par->bplcon0 & BPC0_LACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) sspr = shfsprite + (delta << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) sspr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) for (height = (short)var->height - 1; height >= 0; height--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) bits = 0; words = delta; datawords = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) for (width = (short)var->width - 1; width >= 0; width--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (bits == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) bits = 16; --words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) asm volatile ("movew %1@(%3:w:2),%0 ; swap %0 ; movew %1@+,%0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) : "=d" (datawords), "=a" (lspr) : "1" (lspr), "d" (delta));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) datawords = (*(lspr + delta) << 16) | (*lspr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) --bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) "clrb %0 ; swap %1 ; lslw #1,%1 ; roxlb #1,%0 ; "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) "swap %1 ; lslw #1,%1 ; roxlb #1,%0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) : "=d" (color), "=d" (datawords) : "1" (datawords));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) color = (((datawords >> 30) & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) | ((datawords >> 15) & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) datawords <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* FIXME: check the return value + test the change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) put_user(color, data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (bits > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) --words; ++lspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) while (--words >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) ++lspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) asm volatile ("lea %0@(%4:w:2),%0 ; tstl %1 ; jeq 1f ; exg %0,%1\n1:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) : "=a" (lspr), "=a" (sspr) : "0" (lspr), "1" (sspr), "d" (delta));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) lspr += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (sspr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) u_short *tmp = lspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) lspr = sspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) sspr = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static int ami_set_var_cursorinfo(struct fb_var_cursorinfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) u_char __user *data, struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) register u_short *lspr, *sspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) register u_long datawords asm ("d2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) register u_long datawords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) register short delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) u_short fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) short height, width, bits, words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (!var->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) else if (var->width <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) fmode = TAG_FMODE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) else if (var->width <= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) fmode = TAG_FMODE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) else if (var->width <= 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) fmode = TAG_FMODE_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (fmode > maxfmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (!var->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) delta = 1 << fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) lofsprite = shfsprite = (u_short *)spritememory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) lspr = lofsprite + (delta << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (par->bplcon0 & BPC0_LACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (((var->height + 4) << fmode << 2) > SPRITEMEMSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) memset(lspr, 0, (var->height + 4) << fmode << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) shfsprite += ((var->height + 5)&-2) << fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) sspr = shfsprite + (delta << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (((var->height + 2) << fmode << 2) > SPRITEMEMSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) memset(lspr, 0, (var->height + 2) << fmode << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) sspr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) for (height = (short)var->height - 1; height >= 0; height--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) bits = 16; words = delta; datawords = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) for (width = (short)var->width - 1; width >= 0; width--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) unsigned long tdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* FIXME: check the return value + test the change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) get_user(tdata, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) "lsrb #1,%2 ; roxlw #1,%0 ; swap %0 ; "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) "lsrb #1,%2 ; roxlw #1,%0 ; swap %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) : "=d" (datawords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) : "0" (datawords), "d" (tdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) datawords = ((datawords << 1) & 0xfffefffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) datawords |= tdata & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) datawords |= (tdata & 2) << (16 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (--bits == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) bits = 16; --words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) asm volatile ("swap %2 ; movew %2,%0@(%3:w:2) ; swap %2 ; movew %2,%0@+"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) : "=a" (lspr) : "0" (lspr), "d" (datawords), "d" (delta));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) *(lspr + delta) = (u_short) (datawords >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) *lspr++ = (u_short) (datawords & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (bits < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) --words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) "swap %2 ; lslw %4,%2 ; movew %2,%0@(%3:w:2) ; "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) "swap %2 ; lslw %4,%2 ; movew %2,%0@+"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) : "=a" (lspr) : "0" (lspr), "d" (datawords), "d" (delta), "d" (bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) *(lspr + delta) = (u_short) (datawords >> (16 + bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) *lspr++ = (u_short) ((datawords & 0x0000ffff) >> bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) while (--words >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) asm volatile ("moveql #0,%%d0 ; movew %%d0,%0@(%2:w:2) ; movew %%d0,%0@+"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) : "=a" (lspr) : "0" (lspr), "d" (delta) : "d0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) *(lspr + delta) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) *lspr++ = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) #ifdef __mc68000__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) asm volatile ("lea %0@(%4:w:2),%0 ; tstl %1 ; jeq 1f ; exg %0,%1\n1:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) : "=a" (lspr), "=a" (sspr) : "0" (lspr), "1" (sspr), "d" (delta));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) lspr += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if (sspr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) u_short *tmp = lspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) lspr = sspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) sspr = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) par->crsr.height = var->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) par->crsr.width = var->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) par->crsr.spot_x = var->xspot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) par->crsr.spot_y = var->yspot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) par->crsr.fmode = fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (IS_AGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) par->fmode &= ~(FMODE_SPAGEM | FMODE_SPR32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) par->fmode |= sprfetchmode[fmode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) custom.fmode = par->fmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static int ami_get_cursorstate(struct fb_cursorstate *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) state->xoffset = par->crsr.crsr_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) state->yoffset = par->crsr.crsr_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) state->mode = cursormode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static int ami_set_cursorstate(struct fb_cursorstate *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) par->crsr.crsr_x = state->xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) par->crsr.crsr_y = state->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if ((cursormode = state->mode) == FB_CURSOR_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) cursorstate = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) do_cursor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static void ami_set_sprite(const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) copins *copl, *cops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) u_short hs, vs, ve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) u_long pl, ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) short mx, my;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) cops = copdisplay.list[currentcop][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) copl = copdisplay.list[currentcop][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ps = pl = ZTWO_PADDR(dummysprite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) mx = par->crsr.crsr_x - par->crsr.spot_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) my = par->crsr.crsr_y - par->crsr.spot_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (!(par->vmode & FB_VMODE_YWRAP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) mx -= par->xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) my -= par->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (!is_blanked && cursorstate > 0 && par->crsr.height > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) mx > -(short)par->crsr.width && mx < par->xres &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) my > -(short)par->crsr.height && my < par->yres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) pl = ZTWO_PADDR(lofsprite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) hs = par->diwstrt_h + (mx << par->clk_shift) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) vs = par->diwstrt_v + (my << par->line_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) ve = vs + (par->crsr.height << par->line_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (par->bplcon0 & BPC0_LACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) ps = ZTWO_PADDR(shfsprite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) lofsprite[0] = spr2hw_pos(vs, hs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) shfsprite[0] = spr2hw_pos(vs + 1, hs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (mod2(vs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) shfsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs + 1, hs, ve + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) swap(pl, ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) shfsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs + 1, hs, ve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) lofsprite[0] = spr2hw_pos(vs, hs) | (IS_AGA && (par->fmode & FMODE_BSCAN2) ? 0x80 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) copl[cop_spr0ptrh].w[1] = highw(pl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) copl[cop_spr0ptrl].w[1] = loww(pl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (par->bplcon0 & BPC0_LACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) cops[cop_spr0ptrh].w[1] = highw(ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) cops[cop_spr0ptrl].w[1] = loww(ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) * Initialise the Copper Initialisation List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static void __init ami_init_copper(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) copins *cop = copdisplay.init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) u_long p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) (cop++)->l = CMOVE(BPC0_COLOR | BPC0_SHRES | BPC0_ECSENA, bplcon0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) (cop++)->l = CMOVE(0x0181, diwstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) (cop++)->l = CMOVE(0x0281, diwstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) (cop++)->l = CMOVE(0x0000, diwhigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) (cop++)->l = CMOVE(BPC0_COLOR, bplcon0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) p = ZTWO_PADDR(dummysprite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) (cop++)->l = CMOVE(0, spr[i].pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) (cop++)->l = CMOVE(highw(p), sprpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) (cop++)->l = CMOVE2(loww(p), sprpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) (cop++)->l = CMOVE(IF_SETCLR | IF_COPER, intreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) copdisplay.wait = cop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) (cop++)->l = CEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) (cop++)->l = CMOVE(0, copjmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) cop->l = CEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) custom.cop1lc = (u_short *)ZTWO_PADDR(copdisplay.init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) custom.copjmp1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) static void ami_reinit_copper(const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) copdisplay.init[cip_bplcon0].w[1] = ~(BPC0_BPU3 | BPC0_BPU2 | BPC0_BPU1 | BPC0_BPU0) & par->bplcon0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) copdisplay.wait->l = CWAIT(32, par->diwstrt_v - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * Rebuild the Copper List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * We only change the things that are not static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) static void ami_rebuild_copper(const struct amifb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) copins *copl, *cops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) u_short line, h_end1, h_end2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) short i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) u_long p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (IS_AGA && maxfmode + par->clk_shift == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) h_end1 = par->diwstrt_h - 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) h_end1 = par->htotal - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) h_end2 = par->ddfstop + 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) ami_set_sprite(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) copl = copdisplay.rebuild[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) p = par->bplpt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (par->vmode & FB_VMODE_YWRAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if ((par->vyres - par->yoffset) != 1 || !mod2(par->diwstrt_v)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (par->yoffset > par->vyres - par->yres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) (copl++)->l = CMOVE(highw(p), bplpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) (copl++)->l = CMOVE2(loww(p), bplpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) line = par->diwstrt_v + ((par->vyres - par->yoffset) << par->line_shift) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) while (line >= 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) (copl++)->l = CWAIT(h_end1, 510);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) line -= 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (line >= 510 && IS_AGA && maxfmode + par->clk_shift == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) (copl++)->l = CWAIT(h_end1, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) (copl++)->l = CWAIT(h_end2, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) p = par->bplpt0wrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) p = par->bplpt0wrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) (copl++)->l = CMOVE(highw(p), bplpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) (copl++)->l = CMOVE2(loww(p), bplpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) copl->l = CEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (par->bplcon0 & BPC0_LACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) cops = copdisplay.rebuild[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) p = par->bplpt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) if (mod2(par->diwstrt_v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) p -= par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) p += par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) if (par->vmode & FB_VMODE_YWRAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if ((par->vyres - par->yoffset) != 1 || mod2(par->diwstrt_v)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) if (par->yoffset > par->vyres - par->yres + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) (cops++)->l = CMOVE(highw(p), bplpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) (cops++)->l = CMOVE2(loww(p), bplpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) line = par->diwstrt_v + ((par->vyres - par->yoffset) << par->line_shift) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) while (line >= 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) (cops++)->l = CWAIT(h_end1, 510);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) line -= 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (line > 510 && IS_AGA && maxfmode + par->clk_shift == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) (cops++)->l = CWAIT(h_end1, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) (cops++)->l = CWAIT(h_end2, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) p = par->bplpt0wrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (mod2(par->diwstrt_v + par->vyres -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) par->yoffset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) p -= par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) p += par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) p = par->bplpt0wrap - par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) (cops++)->l = CMOVE(highw(p), bplpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) (cops++)->l = CMOVE2(loww(p), bplpt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) cops->l = CEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) * Build the Copper List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static void ami_build_copper(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) struct amifb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) copins *copl, *cops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) u_long p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) currentcop = 1 - currentcop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) copl = copdisplay.list[currentcop][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) (copl++)->l = CWAIT(0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) (copl++)->l = CMOVE(par->bplcon0, bplcon0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) (copl++)->l = CMOVE(0, sprpt[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) (copl++)->l = CMOVE2(0, sprpt[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (par->bplcon0 & BPC0_LACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) cops = copdisplay.list[currentcop][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) (cops++)->l = CWAIT(0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) (cops++)->l = CMOVE(par->bplcon0, bplcon0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) (cops++)->l = CMOVE(0, sprpt[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) (cops++)->l = CMOVE2(0, sprpt[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) (copl++)->l = CMOVE(diwstrt2hw(par->diwstrt_h, par->diwstrt_v + 1), diwstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) (copl++)->l = CMOVE(diwstop2hw(par->diwstop_h, par->diwstop_v + 1), diwstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) (cops++)->l = CMOVE(diwstrt2hw(par->diwstrt_h, par->diwstrt_v), diwstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) (cops++)->l = CMOVE(diwstop2hw(par->diwstop_h, par->diwstop_v), diwstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) (copl++)->l = CMOVE(diwhigh2hw(par->diwstrt_h, par->diwstrt_v + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) par->diwstop_h, par->diwstop_v + 1), diwhigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) (cops++)->l = CMOVE(diwhigh2hw(par->diwstrt_h, par->diwstrt_v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) par->diwstop_h, par->diwstop_v), diwhigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (par->beamcon0 & BMC0_VARBEAMEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) (copl++)->l = CMOVE(vtotal2hw(par->vtotal), vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) (copl++)->l = CMOVE(vbstrt2hw(par->vbstrt + 1), vbstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) (copl++)->l = CMOVE(vbstop2hw(par->vbstop + 1), vbstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) (cops++)->l = CMOVE(vtotal2hw(par->vtotal), vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) (cops++)->l = CMOVE(vbstrt2hw(par->vbstrt), vbstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) (cops++)->l = CMOVE(vbstop2hw(par->vbstop), vbstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) p = ZTWO_PADDR(copdisplay.list[currentcop][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) (copl++)->l = CMOVE(highw(p), cop2lc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) (copl++)->l = CMOVE2(loww(p), cop2lc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) p = ZTWO_PADDR(copdisplay.list[currentcop][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) (cops++)->l = CMOVE(highw(p), cop2lc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) (cops++)->l = CMOVE2(loww(p), cop2lc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) copdisplay.rebuild[0] = cops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) (copl++)->l = CMOVE(diwstrt2hw(par->diwstrt_h, par->diwstrt_v), diwstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) (copl++)->l = CMOVE(diwstop2hw(par->diwstop_h, par->diwstop_v), diwstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (!IS_OCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) (copl++)->l = CMOVE(diwhigh2hw(par->diwstrt_h, par->diwstrt_v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) par->diwstop_h, par->diwstop_v), diwhigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) if (par->beamcon0 & BMC0_VARBEAMEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) (copl++)->l = CMOVE(vtotal2hw(par->vtotal), vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) (copl++)->l = CMOVE(vbstrt2hw(par->vbstrt), vbstrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) (copl++)->l = CMOVE(vbstop2hw(par->vbstop), vbstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) copdisplay.rebuild[1] = copl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) ami_update_par(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) ami_rebuild_copper(info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) static void __init amifb_setup_mcap(char *spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) int vmin, vmax, hmin, hmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) /* Format for monitor capabilities is: <Vmin>;<Vmax>;<Hmin>;<Hmax>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) * <V*> vertical freq. in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) * <H*> horizontal freq. in kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) if (!(p = strsep(&spec, ";")) || !*p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) vmin = simple_strtoul(p, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) if (vmin <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) if (!(p = strsep(&spec, ";")) || !*p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) vmax = simple_strtoul(p, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) if (vmax <= 0 || vmax <= vmin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) if (!(p = strsep(&spec, ";")) || !*p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) hmin = 1000 * simple_strtoul(p, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (hmin <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) if (!(p = strsep(&spec, "")) || !*p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) hmax = 1000 * simple_strtoul(p, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) if (hmax <= 0 || hmax <= hmin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) amifb_hfmin = hmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) amifb_hfmax = hmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) amifb_vfmin = vmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) amifb_vfmax = vmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) static int __init amifb_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) char *this_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) while ((this_opt = strsep(&options, ",")) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (!*this_opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (!strcmp(this_opt, "inverse")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) fb_invert_cmaps();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) } else if (!strcmp(this_opt, "ilbm"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) amifb_ilbm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) else if (!strncmp(this_opt, "monitorcap:", 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) amifb_setup_mcap(this_opt + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) else if (!strncmp(this_opt, "fstart:", 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) min_fstrt = simple_strtoul(this_opt + 7, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) mode_option = this_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (min_fstrt < 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) min_fstrt = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) static int amifb_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) struct amifb_par par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) /* Validate wanted screen parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) err = ami_decode_var(var, &par, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /* Encode (possibly rounded) screen parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) ami_encode_var(var, &par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) static int amifb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) struct amifb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) do_vmode_pan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) do_vmode_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) /* Decode wanted screen parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) error = ami_decode_var(&info->var, par, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /* Set new videomode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) ami_build_copper(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) /* Set VBlank trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) do_vmode_full = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* Update fix for new screen parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) if (par->bpp == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) info->fix.type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) info->fix.type_aux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) } else if (amifb_ilbm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) info->fix.type = FB_TYPE_INTERLEAVED_PLANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) info->fix.type_aux = par->next_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) info->fix.type = FB_TYPE_PLANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) info->fix.type_aux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) info->fix.line_length = div8(upx(16 << maxfmode, par->vxres));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) if (par->vmode & FB_VMODE_YWRAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) info->fix.ywrapstep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) info->fix.xpanstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) info->fix.ypanstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YWRAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) FBINFO_READS_FAST; /* override SCROLL_REDRAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) info->fix.ywrapstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) if (par->vmode & FB_VMODE_SMOOTH_XPAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) info->fix.xpanstep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) info->fix.xpanstep = 16 << maxfmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) info->fix.ypanstep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * Set a single color register. The values supplied are already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * rounded down to the hardware's capabilities (according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) * entries in the var structure). Return != 0 for invalid regno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static int amifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) u_int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) const struct amifb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (IS_AGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) if (regno > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) } else if (par->bplcon0 & BPC0_SHRES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) if (regno > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (regno > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) red >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) green >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) blue >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) if (!regno) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) red0 = red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) green0 = green;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) blue0 = blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) * Update the corresponding Hardware Color Register, unless it's Color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) * Register 0 and the screen is blanked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) * VBlank is switched off to protect bplcon3 or ecs_palette[] from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) * being changed by ami_do_blank() during the VBlank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) if (regno || !is_blanked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) #if defined(CONFIG_FB_AMIGA_AGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) if (IS_AGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) u_short bplcon3 = par->bplcon3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) VBlankOff();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) custom.bplcon3 = bplcon3 | (regno << 8 & 0xe000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) custom.color[regno & 31] = rgb2hw8_high(red, green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) custom.bplcon3 = bplcon3 | (regno << 8 & 0xe000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) BPC3_LOCT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) custom.color[regno & 31] = rgb2hw8_low(red, green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) custom.bplcon3 = bplcon3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) VBlankOn();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #if defined(CONFIG_FB_AMIGA_ECS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) if (par->bplcon0 & BPC0_SHRES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) u_short color, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) mask = 0x3333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) color = rgb2hw2(red, green, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) VBlankOff();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) for (i = regno + 12; i >= (int)regno; i -= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) mask <<= 2; color >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) regno = down16(regno) + mul4(mod4(regno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) for (i = regno + 3; i >= (int)regno; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) VBlankOn();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) custom.color[regno] = rgb2hw4(red, green, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) * Blank the display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) static int amifb_blank(int blank, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) do_blank = blank ? blank : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) * Pan or Wrap the Display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) static int amifb_pan_display(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) if (var->vmode & FB_VMODE_YWRAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (var->yoffset < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) var->yoffset >= info->var.yres_virtual || var->xoffset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) * TODO: There will be problems when xpan!=1, so some columns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) * on the right side will never be seen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if (var->xoffset + info->var.xres >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) upx(16 << maxfmode, info->var.xres_virtual) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) var->yoffset + info->var.yres > info->var.yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) ami_pan_var(var, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) info->var.xoffset = var->xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) info->var.yoffset = var->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) if (var->vmode & FB_VMODE_YWRAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) info->var.vmode |= FB_VMODE_YWRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) info->var.vmode &= ~FB_VMODE_YWRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) #if BITS_PER_LONG == 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) #define BYTES_PER_LONG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) #define SHIFT_PER_LONG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) #elif BITS_PER_LONG == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) #define BYTES_PER_LONG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) #define SHIFT_PER_LONG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) #define Please update me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) * Compose two values, using a bitmask as decision value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) * This is equivalent to (a & mask) | (b & ~mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static inline unsigned long comp(unsigned long a, unsigned long b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) return ((a ^ b) & mask) ^ b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) static inline unsigned long xor(unsigned long a, unsigned long b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) return (a & mask) ^ b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) * Unaligned forward bit copy using 32-bit or 64-bit memory accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) static void bitcpy(unsigned long *dst, int dst_idx, const unsigned long *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) int src_idx, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) unsigned long first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) int shift = dst_idx - src_idx, left, right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) unsigned long d0, d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (!n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) shift = dst_idx - src_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) first = ~0UL >> dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) last = ~(~0UL >> ((dst_idx + n) % BITS_PER_LONG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (!shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) // Same alignment for source and dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (dst_idx + n <= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) // Single word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) first &= last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) *dst = comp(*src, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) // Multiple destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) // Leading bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) *dst = comp(*src, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) n -= BITS_PER_LONG - dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) // Main chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) n /= BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) while (n >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) n -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) while (n--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) *dst++ = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) // Trailing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) *dst = comp(*src, *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) // Different alignment for source and dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) right = shift & (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) left = -shift & (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (dst_idx + n <= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) // Single destination word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) first &= last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) if (shift > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) *dst = comp(*src >> right, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) } else if (src_idx + n <= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) *dst = comp(*src << left, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) d0 = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) d1 = *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) *dst = comp(d0 << left | d1 >> right, *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) // Multiple destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) d0 = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) // Leading bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) if (shift > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) *dst = comp(d0 >> right, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) n -= BITS_PER_LONG - dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) d1 = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) *dst = comp(d0 << left | d1 >> right, *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) n -= BITS_PER_LONG - dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) // Main chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) m = n % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) n /= BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) while (n >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) d1 = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) d1 = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) d1 = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) d1 = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) n -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) while (n--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) d1 = *src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) // Trailing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) if (last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) if (m <= right) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) *dst = comp(d0 << left, *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) d1 = *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) *dst = comp(d0 << left | d1 >> right,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) * Unaligned reverse bit copy using 32-bit or 64-bit memory accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) static void bitcpy_rev(unsigned long *dst, int dst_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) const unsigned long *src, int src_idx, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) unsigned long first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) int shift = dst_idx - src_idx, left, right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) unsigned long d0, d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) if (!n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) dst += (n - 1) / BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) src += (n - 1) / BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) if ((n - 1) % BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) dst_idx += (n - 1) % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) dst += dst_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) dst_idx &= BITS_PER_LONG - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) src_idx += (n - 1) % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) src += src_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) src_idx &= BITS_PER_LONG - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) shift = dst_idx - src_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) first = ~0UL << (BITS_PER_LONG - 1 - dst_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) last = ~(~0UL << (BITS_PER_LONG - 1 - ((dst_idx - n) % BITS_PER_LONG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) if (!shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) // Same alignment for source and dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) if ((unsigned long)dst_idx + 1 >= n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) // Single word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) first &= last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) *dst = comp(*src, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) // Multiple destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) // Leading bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) *dst = comp(*src, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) dst--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) n -= dst_idx + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) // Main chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) n /= BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) while (n >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) n -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) while (n--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) *dst-- = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) // Trailing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) *dst = comp(*src, *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) // Different alignment for source and dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) right = shift & (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) left = -shift & (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) if ((unsigned long)dst_idx + 1 >= n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) // Single destination word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) first &= last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) if (shift < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) *dst = comp(*src << left, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) } else if (1 + (unsigned long)src_idx >= n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) *dst = comp(*src >> right, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) d0 = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) d1 = *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) *dst = comp(d0 >> right | d1 << left, *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) // Multiple destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) d0 = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) // Leading bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) if (shift < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) *dst = comp(d0 << left, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) dst--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) n -= dst_idx + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) d1 = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) *dst = comp(d0 >> right | d1 << left, *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) dst--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) n -= dst_idx + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) // Main chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) m = n % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) n /= BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) while (n >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) d1 = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) *dst-- = d0 >> right | d1 << left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) d1 = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) *dst-- = d0 >> right | d1 << left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) d1 = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) *dst-- = d0 >> right | d1 << left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) d1 = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) *dst-- = d0 >> right | d1 << left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) n -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) while (n--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) d1 = *src--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) *dst-- = d0 >> right | d1 << left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) // Trailing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) if (last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) if (m <= left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) *dst = comp(d0 >> right, *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) d1 = *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) *dst = comp(d0 >> right | d1 << left,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) * Unaligned forward inverting bit copy using 32-bit or 64-bit memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) * accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) static void bitcpy_not(unsigned long *dst, int dst_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) const unsigned long *src, int src_idx, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) unsigned long first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) int shift = dst_idx - src_idx, left, right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) unsigned long d0, d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) if (!n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) shift = dst_idx - src_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) first = ~0UL >> dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) last = ~(~0UL >> ((dst_idx + n) % BITS_PER_LONG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) if (!shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) // Same alignment for source and dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) if (dst_idx + n <= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) // Single word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) first &= last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) *dst = comp(~*src, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) // Multiple destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) // Leading bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) *dst = comp(~*src, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) n -= BITS_PER_LONG - dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) // Main chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) n /= BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) while (n >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) n -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) while (n--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) *dst++ = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) // Trailing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) *dst = comp(~*src, *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) // Different alignment for source and dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) right = shift & (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) left = -shift & (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) if (dst_idx + n <= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) // Single destination word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) first &= last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) if (shift > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) *dst = comp(~*src >> right, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) } else if (src_idx + n <= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) *dst = comp(~*src << left, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) d0 = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) d1 = ~*src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) *dst = comp(d0 << left | d1 >> right, *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) // Multiple destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) d0 = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) // Leading bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) if (shift > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) *dst = comp(d0 >> right, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) n -= BITS_PER_LONG - dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) d1 = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) *dst = comp(d0 << left | d1 >> right, *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) n -= BITS_PER_LONG - dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) // Main chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) m = n % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) n /= BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) while (n >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) d1 = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) d1 = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) d1 = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) d1 = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) n -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) while (n--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) d1 = ~*src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) *dst++ = d0 << left | d1 >> right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) d0 = d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) // Trailing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) if (last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) if (m <= right) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) // Single source word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) *dst = comp(d0 << left, *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) // 2 source words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) d1 = ~*src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) *dst = comp(d0 << left | d1 >> right,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) * Unaligned 32-bit pattern fill using 32/64-bit memory accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) static void bitfill32(unsigned long *dst, int dst_idx, u32 pat, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) unsigned long val = pat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) unsigned long first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) if (!n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) #if BITS_PER_LONG == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) val |= val << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) first = ~0UL >> dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) last = ~(~0UL >> ((dst_idx + n) % BITS_PER_LONG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) if (dst_idx + n <= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) // Single word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) first &= last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) *dst = comp(val, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) // Multiple destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) // Leading bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) *dst = comp(val, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) n -= BITS_PER_LONG - dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) // Main chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) n /= BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) while (n >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) n -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) while (n--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) *dst++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) // Trailing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) *dst = comp(val, *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) * Unaligned 32-bit pattern xor using 32/64-bit memory accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) static void bitxor32(unsigned long *dst, int dst_idx, u32 pat, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) unsigned long val = pat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) unsigned long first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) if (!n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) #if BITS_PER_LONG == 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) val |= val << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) first = ~0UL >> dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) last = ~(~0UL >> ((dst_idx + n) % BITS_PER_LONG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if (dst_idx + n <= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) // Single word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) first &= last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) *dst = xor(val, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) // Multiple destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) // Leading bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) *dst = xor(val, *dst, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) n -= BITS_PER_LONG - dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) // Main chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) n /= BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) while (n >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) *dst++ ^= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) *dst++ ^= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) *dst++ ^= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) *dst++ ^= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) n -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) while (n--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) *dst++ ^= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) // Trailing bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) *dst = xor(val, *dst, last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) static inline void fill_one_line(int bpp, unsigned long next_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) unsigned long *dst, int dst_idx, u32 n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) u32 color)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) dst += dst_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) dst_idx &= (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) bitfill32(dst, dst_idx, color & 1 ? ~0 : 0, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) if (!--bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) color >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) dst_idx += next_plane * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) static inline void xor_one_line(int bpp, unsigned long next_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) unsigned long *dst, int dst_idx, u32 n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) u32 color)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) while (color) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) dst += dst_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) dst_idx &= (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) bitxor32(dst, dst_idx, color & 1 ? ~0 : 0, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) if (!--bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) color >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) dst_idx += next_plane * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) static void amifb_fillrect(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) const struct fb_fillrect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) struct amifb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) int dst_idx, x2, y2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) unsigned long *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) u32 width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) if (!rect->width || !rect->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) * We could use hardware clipping but on many cards you get around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) * hardware clipping by writing to framebuffer directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) x2 = rect->dx + rect->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) y2 = rect->dy + rect->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) width = x2 - rect->dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) height = y2 - rect->dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) dst = (unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) ((unsigned long)info->screen_base & ~(BYTES_PER_LONG - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) dst_idx = ((unsigned long)info->screen_base & (BYTES_PER_LONG - 1)) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) dst_idx += rect->dy * par->next_line * 8 + rect->dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) while (height--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) switch (rect->rop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) case ROP_COPY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) fill_one_line(info->var.bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) par->next_plane, dst, dst_idx, width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) rect->color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) case ROP_XOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) xor_one_line(info->var.bits_per_pixel, par->next_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) dst, dst_idx, width, rect->color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) dst_idx += par->next_line * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) static inline void copy_one_line(int bpp, unsigned long next_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) unsigned long *dst, int dst_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) unsigned long *src, int src_idx, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) dst += dst_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) dst_idx &= (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) src += src_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) src_idx &= (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) bitcpy(dst, dst_idx, src, src_idx, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) if (!--bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) dst_idx += next_plane * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) src_idx += next_plane * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) static inline void copy_one_line_rev(int bpp, unsigned long next_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) unsigned long *dst, int dst_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) unsigned long *src, int src_idx, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) dst += dst_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) dst_idx &= (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) src += src_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) src_idx &= (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) bitcpy_rev(dst, dst_idx, src, src_idx, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) if (!--bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) dst_idx += next_plane * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) src_idx += next_plane * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) static void amifb_copyarea(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) const struct fb_copyarea *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) struct amifb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) int x2, y2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) u32 dx, dy, sx, sy, width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) unsigned long *dst, *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) int dst_idx, src_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) int rev_copy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) /* clip the destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) x2 = area->dx + area->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) y2 = area->dy + area->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) dx = area->dx > 0 ? area->dx : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) dy = area->dy > 0 ? area->dy : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) width = x2 - dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) height = y2 - dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) if (area->sx + dx < area->dx || area->sy + dy < area->dy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) /* update sx,sy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) sx = area->sx + (dx - area->dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) sy = area->sy + (dy - area->dy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) /* the source must be completely inside the virtual screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) if (sx + width > info->var.xres_virtual ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) sy + height > info->var.yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) if (dy > sy || (dy == sy && dx > sx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) dy += height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) sy += height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) rev_copy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) dst = (unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) ((unsigned long)info->screen_base & ~(BYTES_PER_LONG - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) src = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) dst_idx = ((unsigned long)info->screen_base & (BYTES_PER_LONG - 1)) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) src_idx = dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) dst_idx += dy * par->next_line * 8 + dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) src_idx += sy * par->next_line * 8 + sx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) if (rev_copy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) while (height--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) dst_idx -= par->next_line * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) src_idx -= par->next_line * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) copy_one_line_rev(info->var.bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) par->next_plane, dst, dst_idx, src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) src_idx, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) while (height--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) copy_one_line(info->var.bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) par->next_plane, dst, dst_idx, src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) src_idx, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) dst_idx += par->next_line * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) src_idx += par->next_line * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) static inline void expand_one_line(int bpp, unsigned long next_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) unsigned long *dst, int dst_idx, u32 n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) const u8 *data, u32 bgcolor, u32 fgcolor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) const unsigned long *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) int src_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) dst += dst_idx >> SHIFT_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) dst_idx &= (BITS_PER_LONG - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) if ((bgcolor ^ fgcolor) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) src = (unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) ((unsigned long)data & ~(BYTES_PER_LONG - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) src_idx = ((unsigned long)data & (BYTES_PER_LONG - 1)) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) if (fgcolor & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) bitcpy(dst, dst_idx, src, src_idx, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) bitcpy_not(dst, dst_idx, src, src_idx, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) /* set or clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) bitfill32(dst, dst_idx, fgcolor & 1 ? ~0 : 0, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) if (!--bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) bgcolor >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) fgcolor >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) dst_idx += next_plane * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) static void amifb_imageblit(struct fb_info *info, const struct fb_image *image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) struct amifb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) int x2, y2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) unsigned long *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) int dst_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) const char *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) u32 dx, dy, width, height, pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) * We could use hardware clipping but on many cards you get around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) * hardware clipping by writing to framebuffer directly like we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) * doing here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) x2 = image->dx + image->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) y2 = image->dy + image->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) dx = image->dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) dy = image->dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) width = x2 - dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) height = y2 - dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) if (image->depth == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) dst = (unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) ((unsigned long)info->screen_base & ~(BYTES_PER_LONG - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) dst_idx = ((unsigned long)info->screen_base & (BYTES_PER_LONG - 1)) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) dst_idx += dy * par->next_line * 8 + dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) src = image->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) pitch = (image->width + 7) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) while (height--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) expand_one_line(info->var.bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) par->next_plane, dst, dst_idx, width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) src, image->bg_color,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) image->fg_color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) dst_idx += par->next_line * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) src += pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) c2p_planar(info->screen_base, image->data, dx, dy, width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) height, par->next_line, par->next_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) image->width, info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) * Amiga Frame Buffer Specific ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) static int amifb_ioctl(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) struct fb_fix_cursorinfo fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) struct fb_var_cursorinfo var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) struct fb_cursorstate state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) } crsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) case FBIOGET_FCURSORINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) i = ami_get_fix_cursorinfo(&crsr.fix, info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) return copy_to_user(argp, &crsr.fix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) sizeof(crsr.fix)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) case FBIOGET_VCURSORINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) i = ami_get_var_cursorinfo(&crsr.var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) ((struct fb_var_cursorinfo __user *)arg)->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) return copy_to_user(argp, &crsr.var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) sizeof(crsr.var)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) case FBIOPUT_VCURSORINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) if (copy_from_user(&crsr.var, argp, sizeof(crsr.var)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) return ami_set_var_cursorinfo(&crsr.var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) ((struct fb_var_cursorinfo __user *)arg)->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) case FBIOGET_CURSORSTATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) i = ami_get_cursorstate(&crsr.state, info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) return copy_to_user(argp, &crsr.state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) sizeof(crsr.state)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) case FBIOPUT_CURSORSTATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) if (copy_from_user(&crsr.state, argp, sizeof(crsr.state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) return ami_set_cursorstate(&crsr.state, info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) * Flash the cursor (called by VBlank interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) static int flash_cursor(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) static int cursorcount = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) if (cursormode == FB_CURSOR_FLASH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) if (!--cursorcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) cursorstate = -cursorstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) cursorcount = cursorrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) if (!is_blanked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) * VBlank Display Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) static irqreturn_t amifb_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) struct amifb_par *par = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) if (do_vmode_pan || do_vmode_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) ami_update_display(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) if (do_vmode_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) ami_init_display(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) if (do_vmode_pan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) flash_cursor();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) ami_rebuild_copper(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) do_cursor = do_vmode_pan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) } else if (do_cursor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) flash_cursor();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) ami_set_sprite(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) do_cursor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) if (flash_cursor())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) ami_set_sprite(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) if (do_blank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) ami_do_blank(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) do_blank = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) if (do_vmode_full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) ami_reinit_copper(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) do_vmode_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) static const struct fb_ops amifb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) .fb_check_var = amifb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) .fb_set_par = amifb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) .fb_setcolreg = amifb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) .fb_blank = amifb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) .fb_pan_display = amifb_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) .fb_fillrect = amifb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) .fb_copyarea = amifb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) .fb_imageblit = amifb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) .fb_ioctl = amifb_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) * Allocate, Clear and Align a Block of Chip Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) static void *aligned_chipptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) static inline u_long __init chipalloc(u_long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) aligned_chipptr = amiga_chip_alloc(size, "amifb [RAM]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) if (!aligned_chipptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) pr_err("amifb: No Chip RAM for frame buffer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) memset(aligned_chipptr, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) return (u_long)aligned_chipptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) static inline void chipfree(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) if (aligned_chipptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) amiga_chip_free(aligned_chipptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) * Initialisation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) static int __init amifb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) int tag, i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) u_long chipptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) u_int defmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) char *option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) if (fb_get_options("amifb", &option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) amifb_video_off();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) amifb_setup(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) custom.dmacon = DMAF_ALL | DMAF_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) info = framebuffer_alloc(sizeof(struct amifb_par), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) strcpy(info->fix.id, "Amiga ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) info->fix.accel = FB_ACCEL_AMIGABLITT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) switch (amiga_chipset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) #ifdef CONFIG_FB_AMIGA_OCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) case CS_OCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) strcat(info->fix.id, "OCS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) default_chipset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) chipset = TAG_OCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) maxdepth[TAG_SHRES] = 0; /* OCS means no SHRES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) maxdepth[TAG_HIRES] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) maxdepth[TAG_LORES] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) maxfmode = TAG_FMODE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) defmode = amiga_vblank == 50 ? DEFMODE_PAL : DEFMODE_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) info->fix.smem_len = VIDEOMEMSIZE_OCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) #endif /* CONFIG_FB_AMIGA_OCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) #ifdef CONFIG_FB_AMIGA_ECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) case CS_ECS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) strcat(info->fix.id, "ECS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) chipset = TAG_ECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) maxdepth[TAG_SHRES] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) maxdepth[TAG_HIRES] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) maxdepth[TAG_LORES] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) maxfmode = TAG_FMODE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) if (AMIGAHW_PRESENT(AMBER_FF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) defmode = amiga_vblank == 50 ? DEFMODE_AMBER_PAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) : DEFMODE_AMBER_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) defmode = amiga_vblank == 50 ? DEFMODE_PAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) : DEFMODE_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) if (amiga_chip_avail() - CHIPRAM_SAFETY_LIMIT >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) VIDEOMEMSIZE_ECS_2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) info->fix.smem_len = VIDEOMEMSIZE_ECS_2M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) info->fix.smem_len = VIDEOMEMSIZE_ECS_1M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) #endif /* CONFIG_FB_AMIGA_ECS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) #ifdef CONFIG_FB_AMIGA_AGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) case CS_AGA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) strcat(info->fix.id, "AGA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) chipset = TAG_AGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) maxdepth[TAG_SHRES] = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) maxdepth[TAG_HIRES] = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) maxdepth[TAG_LORES] = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) maxfmode = TAG_FMODE_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) defmode = DEFMODE_AGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) if (amiga_chip_avail() - CHIPRAM_SAFETY_LIMIT >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) VIDEOMEMSIZE_AGA_2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) info->fix.smem_len = VIDEOMEMSIZE_AGA_2M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) info->fix.smem_len = VIDEOMEMSIZE_AGA_1M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) #endif /* CONFIG_FB_AMIGA_AGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) #ifdef CONFIG_FB_AMIGA_OCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) printk("Unknown graphics chipset, defaulting to OCS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) strcat(info->fix.id, "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) goto default_chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) #else /* CONFIG_FB_AMIGA_OCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) #endif /* CONFIG_FB_AMIGA_OCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) * Calculate the Pixel Clock Values for this Machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) u_long tmp = DIVUL(200000000000ULL, amiga_eclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) pixclock[TAG_SHRES] = (tmp + 4) / 8; /* SHRES: 35 ns / 28 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) pixclock[TAG_HIRES] = (tmp + 2) / 4; /* HIRES: 70 ns / 14 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) pixclock[TAG_LORES] = (tmp + 1) / 2; /* LORES: 140 ns / 7 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) * Replace the Tag Values with the Real Pixel Clock Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) for (i = 0; i < NUM_TOTAL_MODES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) struct fb_videomode *mode = &ami_modedb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) tag = mode->pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) if (tag == TAG_SHRES || tag == TAG_HIRES || tag == TAG_LORES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) mode->pixclock = pixclock[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) if (amifb_hfmin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) info->monspecs.hfmin = amifb_hfmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) info->monspecs.hfmax = amifb_hfmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) info->monspecs.vfmin = amifb_vfmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) info->monspecs.vfmax = amifb_vfmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) * These are for a typical Amiga monitor (e.g. A1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) info->monspecs.hfmin = 15000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) info->monspecs.hfmax = 38000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) info->monspecs.vfmin = 49;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) info->monspecs.vfmax = 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) info->fbops = &amifb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) info->flags = FBINFO_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) info->device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) if (!fb_find_mode(&info->var, info, mode_option, ami_modedb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) NUM_TOTAL_MODES, &ami_modedb[defmode], 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) fb_videomode_to_modelist(ami_modedb, NUM_TOTAL_MODES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) round_down_bpp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) chipptr = chipalloc(info->fix.smem_len + SPRITEMEMSIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) DUMMYSPRITEMEMSIZE + COPINITSIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) 4 * COPLISTSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) if (!chipptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) assignchunk(videomemory, u_long, chipptr, info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) assignchunk(spritememory, u_long, chipptr, SPRITEMEMSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) assignchunk(dummysprite, u_short *, chipptr, DUMMYSPRITEMEMSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) assignchunk(copdisplay.init, copins *, chipptr, COPINITSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) assignchunk(copdisplay.list[0][0], copins *, chipptr, COPLISTSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) assignchunk(copdisplay.list[0][1], copins *, chipptr, COPLISTSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) assignchunk(copdisplay.list[1][0], copins *, chipptr, COPLISTSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) assignchunk(copdisplay.list[1][1], copins *, chipptr, COPLISTSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) * access the videomem with writethrough cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) info->fix.smem_start = (u_long)ZTWO_PADDR(videomemory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) videomemory = (u_long)ioremap_wt(info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) if (!videomemory) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) "Unable to map videomem cached writethrough\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) info->screen_base = ZTWO_VADDR(info->fix.smem_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) info->screen_base = (char *)videomemory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) memset(dummysprite, 0, DUMMYSPRITEMEMSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) * Make sure the Copper has something to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) ami_init_copper();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) * Enable Display DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) custom.dmacon = DMAF_SETCLR | DMAF_MASTER | DMAF_RASTER | DMAF_COPPER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) DMAF_BLITTER | DMAF_SPRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) err = request_irq(IRQ_AMIGA_COPPER, amifb_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) "fb vertb handler", info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) goto disable_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) err = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) goto free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) dev_set_drvdata(&pdev->dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) err = register_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) goto unset_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) fb_info(info, "%s frame buffer device, using %dK of video memory\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) info->fix.id, info->fix.smem_len>>10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) unset_drvdata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) free_irq(IRQ_AMIGA_COPPER, info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) disable_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) custom.dmacon = DMAF_ALL | DMAF_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) if (videomemory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) iounmap((void *)videomemory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) chipfree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) static int __exit amifb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) struct fb_info *info = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) free_irq(IRQ_AMIGA_COPPER, info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) custom.dmacon = DMAF_ALL | DMAF_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) if (videomemory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) iounmap((void *)videomemory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) chipfree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) amifb_video_off();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) static struct platform_driver amifb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) .remove = __exit_p(amifb_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) .name = "amiga-video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) module_platform_driver_probe(amifb_driver, amifb_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) MODULE_ALIAS("platform:amiga-video");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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