^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/video/backlight/vgg2432a4.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * VGG2432A4 (ILI9320) LCD controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2007 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/lcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <video/ili9320.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ili9320.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Device initialisation sequences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct ili9320_reg vgg_init1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .address = ILI9320_POWER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .value = ILI9320_POWER1_AP(0) | ILI9320_POWER1_BT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .address = ILI9320_POWER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .value = (ILI9320_POWER2_VC(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ILI9320_POWER2_DC0(0) | ILI9320_POWER2_DC1(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .address = ILI9320_POWER3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .value = ILI9320_POWER3_VRH(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .address = ILI9320_POWER4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .value = ILI9320_POWER4_VREOUT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct ili9320_reg vgg_init2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .address = ILI9320_POWER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .value = (ILI9320_POWER1_AP(3) | ILI9320_POWER1_APE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ILI9320_POWER1_BT(7) | ILI9320_POWER1_SAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .address = ILI9320_POWER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .value = ILI9320_POWER2_VC(7) | ILI9320_POWER2_DC0(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct ili9320_reg vgg_gamma[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .address = ILI9320_GAMMA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .value = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .address = ILI9320_GAMMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .value = 0x0505,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .address = ILI9320_GAMMA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .value = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .address = ILI9320_GAMMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .value = 0x0006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .address = ILI9320_GAMMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .value = 0x0707,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .address = ILI9320_GAMMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .value = 0x0105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .address = ILI9320_GAMMA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .value = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .address = ILI9320_GAMMA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .value = 0x0707,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .address = ILI9320_GAMMA9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .value = 0x0704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .address = ILI9320_GAMMA10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .value = 0x807,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct ili9320_reg vgg_init0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* set direction and scan mode gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .address = ILI9320_DRIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .value = ILI9320_DRIVER_SS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .address = ILI9320_DRIVEWAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .value = (ILI9320_DRIVEWAVE_MUSTSET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ILI9320_DRIVEWAVE_EOR | ILI9320_DRIVEWAVE_BC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .address = ILI9320_ENTRYMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .value = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .address = ILI9320_RESIZING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .value = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int vgg2432a4_lcd_init(struct ili9320 *lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct ili9320_platdata *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Set VCore before anything else (VGG243237-6UFLWA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = ili9320_write(lcd, 0x00e5, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto err_initial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Start the oscillator up before we can do anything else. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = ili9320_write(lcd, ILI9320_OSCILATION, ILI9320_OSCILATION_OSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto err_initial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* must wait at-lesat 10ms after starting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mdelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = ili9320_write_regs(lcd, vgg_init0, ARRAY_SIZE(vgg_init0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) goto err_initial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ili9320_write(lcd, ILI9320_DISPLAY2, cfg->display2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ili9320_write(lcd, ILI9320_DISPLAY3, cfg->display3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ili9320_write(lcd, ILI9320_DISPLAY4, cfg->display4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ili9320_write(lcd, ILI9320_RGB_IF1, cfg->rgb_if1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ili9320_write(lcd, ILI9320_FRAMEMAKER, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ili9320_write(lcd, ILI9320_RGB_IF2, cfg->rgb_if2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = ili9320_write_regs(lcd, vgg_init1, ARRAY_SIZE(vgg_init1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) goto err_vgg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mdelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = ili9320_write_regs(lcd, vgg_init2, ARRAY_SIZE(vgg_init2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto err_vgg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ili9320_write(lcd, ILI9320_POWER3, 0x13c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ili9320_write(lcd, ILI9320_POWER4, 0x1c00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ili9320_write(lcd, ILI9320_POWER7, 0x000e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ili9320_write(lcd, ILI9320_GRAM_HORIZ_ADDR, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ili9320_write(lcd, ILI9320_GRAM_VERT_ADD, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = ili9320_write_regs(lcd, vgg_gamma, ARRAY_SIZE(vgg_gamma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto err_vgg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ili9320_write(lcd, ILI9320_HORIZ_START, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ili9320_write(lcd, ILI9320_HORIZ_END, cfg->hsize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ili9320_write(lcd, ILI9320_VERT_START, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ili9320_write(lcd, ILI9320_VERT_END, cfg->vsize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ili9320_write(lcd, ILI9320_DRIVER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ILI9320_DRIVER2_NL(((cfg->vsize - 240) / 8) + 0x1D));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ili9320_write(lcd, ILI9320_BASE_IMAGE, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ili9320_write(lcd, ILI9320_VERT_SCROLL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (addr = ILI9320_PARTIAL1_POSITION; addr <= ILI9320_PARTIAL2_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) addr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ili9320_write(lcd, addr, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ili9320_write(lcd, ILI9320_INTERFACE1, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ili9320_write(lcd, ILI9320_INTERFACE2, cfg->interface2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ili9320_write(lcd, ILI9320_INTERFACE3, cfg->interface3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ili9320_write(lcd, ILI9320_INTERFACE4, cfg->interface4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ili9320_write(lcd, ILI9320_INTERFACE5, cfg->interface5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ili9320_write(lcd, ILI9320_INTERFACE6, cfg->interface6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) lcd->display1 = (ILI9320_DISPLAY1_D(3) | ILI9320_DISPLAY1_DTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ILI9320_DISPLAY1_GON | ILI9320_DISPLAY1_BASEE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ili9320_write(lcd, ILI9320_DISPLAY1, lcd->display1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err_vgg3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) err_vgg2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) err_vgg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) err_initial:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int vgg2432a4_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ili9320_suspend(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int vgg2432a4_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ili9320_resume(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct ili9320_client vgg2432a4_client = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .name = "VGG2432A4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .init = vgg2432a4_lcd_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Device probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int vgg2432a4_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = ili9320_probe_spi(spi, &vgg2432a4_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(&spi->dev, "failed to initialise ili9320\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int vgg2432a4_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ili9320_remove(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void vgg2432a4_shutdown(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ili9320_shutdown(spi_get_drvdata(spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static SIMPLE_DEV_PM_OPS(vgg2432a4_pm_ops, vgg2432a4_suspend, vgg2432a4_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct spi_driver vgg2432a4_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "VGG2432A4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .pm = &vgg2432a4_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .probe = vgg2432a4_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .remove = vgg2432a4_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .shutdown = vgg2432a4_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) module_spi_driver(vgg2432a4_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_AUTHOR("Ben Dooks <ben-linux@fluff.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_DESCRIPTION("VGG2432A4 LCD Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_ALIAS("spi:VGG2432A4");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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