^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for ORISE Technology OTM3225A SOC for TFT LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017, EETS GmbH, Felix Brack <fb@ltec.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This driver implements a lcd device for the ORISE OTM3225A display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * controller. The control interface to the display is SPI and the display's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * memory is updated over the 16-bit RGB interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The main source of information for writing this driver was provided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * OTM3225A datasheet from ORISE Technology. Some information arise from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ILI9328 datasheet from ILITEK as well as from the datasheets and sample code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * provided by Crystalfontz America Inc. who sells the CFAF240320A-032T, a 3.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * TFT LC display using the OTM3225A controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/lcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OTM3225A_INDEX_REG 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OTM3225A_DATA_REG 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* instruction register list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRIVER_OUTPUT_CTRL_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_WAVEFORM_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ENTRY_MODE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SCALING_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DISPLAY_CTRL_1 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DISPLAY_CTRL_2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DISPLAY_CTRL_3 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FRAME_CYCLE_CTRL 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EXT_DISP_IFACE_CTRL_1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FRAME_MAKER_POS 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EXT_DISP_IFACE_CTRL_2 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define POWER_CTRL_1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define POWER_CTRL_2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define POWER_CTRL_3 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define POWER_CTRL_4 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GRAM_ADDR_HORIZ_SET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GRAM_ADDR_VERT_SET 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GRAM_READ_WRITE 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define POWER_CTRL_7 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FRAME_RATE_CTRL 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GAMMA_CTRL_1 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GAMMA_CTRL_2 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GAMMA_CTRL_3 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GAMMA_CTRL_4 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GAMMA_CTRL_5 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GAMMA_CTRL_6 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GAMMA_CTRL_7 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GAMMA_CTRL_8 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GAMMA_CTRL_9 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GAMMA_CTRL_10 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WINDOW_HORIZ_RAM_START 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WINDOW_HORIZ_RAM_END 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WINDOW_VERT_RAM_START 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WINDOW_VERT_RAM_END 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRIVER_OUTPUT_CTRL_2 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BASE_IMG_DISPLAY_CTRL 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VERT_SCROLL_CTRL 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PD1_DISPLAY_POS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PD1_RAM_START 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PD1_RAM_END 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PD2_DISPLAY_POS 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PD2_RAM_START 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PD2_RAM_END 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PANEL_IFACE_CTRL_1 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PANEL_IFACE_CTRL_2 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PANEL_IFACE_CTRL_4 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PANEL_IFACE_CTRL_5 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct otm3225a_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct lcd_device *ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct otm3225a_spi_instruction {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned char reg; /* register to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned short value; /* data to write to 'reg' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned short delay; /* delay in ms after write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct otm3225a_spi_instruction display_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { DRIVER_OUTPUT_CTRL_1, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { DRIVER_WAVEFORM_CTRL, 0x0700, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { ENTRY_MODE, 0x50A0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { SCALING_CTRL, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { DISPLAY_CTRL_2, 0x0606, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { DISPLAY_CTRL_3, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { FRAME_CYCLE_CTRL, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { EXT_DISP_IFACE_CTRL_1, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { FRAME_MAKER_POS, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { EXT_DISP_IFACE_CTRL_2, 0x0002, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { POWER_CTRL_2, 0x0007, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { POWER_CTRL_3, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { POWER_CTRL_4, 0x0000, 200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { DISPLAY_CTRL_1, 0x0101, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { POWER_CTRL_1, 0x12B0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { POWER_CTRL_2, 0x0007, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { POWER_CTRL_3, 0x01BB, 50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { POWER_CTRL_4, 0x0013, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { POWER_CTRL_7, 0x0010, 50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { GAMMA_CTRL_1, 0x000A, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { GAMMA_CTRL_2, 0x1326, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { GAMMA_CTRL_3, 0x0A29, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { GAMMA_CTRL_4, 0x0A0A, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { GAMMA_CTRL_5, 0x1E03, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { GAMMA_CTRL_6, 0x031E, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { GAMMA_CTRL_7, 0x0706, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { GAMMA_CTRL_8, 0x0303, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { GAMMA_CTRL_9, 0x010E, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { GAMMA_CTRL_10, 0x040E, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { WINDOW_HORIZ_RAM_START, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { WINDOW_HORIZ_RAM_END, 0x00EF, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { WINDOW_VERT_RAM_START, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { WINDOW_VERT_RAM_END, 0x013F, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { DRIVER_OUTPUT_CTRL_2, 0x2700, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { BASE_IMG_DISPLAY_CTRL, 0x0001, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { VERT_SCROLL_CTRL, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { PD1_DISPLAY_POS, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { PD1_RAM_START, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { PD1_RAM_END, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { PD2_DISPLAY_POS, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { PD2_RAM_START, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { PD2_RAM_END, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { PANEL_IFACE_CTRL_1, 0x0010, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { PANEL_IFACE_CTRL_2, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { PANEL_IFACE_CTRL_4, 0x0210, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { PANEL_IFACE_CTRL_5, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { DISPLAY_CTRL_1, 0x0133, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct otm3225a_spi_instruction display_enable_rgb_interface[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { ENTRY_MODE, 0x1080, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { GRAM_ADDR_HORIZ_SET, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { GRAM_ADDR_VERT_SET, 0x0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { EXT_DISP_IFACE_CTRL_1, 0x0111, 500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct otm3225a_spi_instruction display_off[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { DISPLAY_CTRL_1, 0x0131, 100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { DISPLAY_CTRL_1, 0x0130, 100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { DISPLAY_CTRL_1, 0x0100, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { POWER_CTRL_1, 0x0280, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { POWER_CTRL_3, 0x018B, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct otm3225a_spi_instruction display_on[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { POWER_CTRL_1, 0x1280, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { DISPLAY_CTRL_1, 0x0101, 100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { DISPLAY_CTRL_1, 0x0121, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { DISPLAY_CTRL_1, 0x0123, 100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { DISPLAY_CTRL_1, 0x0133, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void otm3225a_write(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct otm3225a_spi_instruction *instruction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned char buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* address register using index register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) buf[0] = OTM3225A_INDEX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) buf[2] = instruction->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spi_write(spi, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* write data to addressed register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) buf[0] = OTM3225A_DATA_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) buf[1] = (instruction->value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) buf[2] = instruction->value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) spi_write(spi, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* execute delay if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (instruction->delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) msleep(instruction->delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) instruction++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int otm3225a_set_power(struct lcd_device *ld, int power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct otm3225a_data *dd = lcd_get_data(ld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (power == dd->power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (power > FB_BLANK_UNBLANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) otm3225a_write(dd->spi, display_off, ARRAY_SIZE(display_off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) otm3225a_write(dd->spi, display_on, ARRAY_SIZE(display_on));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dd->power = power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int otm3225a_get_power(struct lcd_device *ld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct otm3225a_data *dd = lcd_get_data(ld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return dd->power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct lcd_ops otm3225a_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .set_power = otm3225a_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .get_power = otm3225a_get_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int otm3225a_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct otm3225a_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct lcd_device *ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dd = devm_kzalloc(dev, sizeof(struct otm3225a_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (dd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ld = devm_lcd_device_register(dev, dev_name(dev), dev, dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) &otm3225a_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (IS_ERR(ld))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return PTR_ERR(ld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dd->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dd->ld = ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_set_drvdata(dev, dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_info(dev, "Initializing and switching to RGB interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) otm3225a_write(spi, display_init, ARRAY_SIZE(display_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) otm3225a_write(spi, display_enable_rgb_interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ARRAY_SIZE(display_enable_rgb_interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct spi_driver otm3225a_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "otm3225a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .probe = otm3225a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) module_spi_driver(otm3225a_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_AUTHOR("Felix Brack <fb@ltec.ch>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_DESCRIPTION("OTM3225A TFT LCD driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_VERSION("1.0.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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