Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Intel IFC VF NIC driver for virtio dataplane offloading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Zhu Lingshan <lingshan.zhu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "ifcvf_base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) static inline u8 ifc_ioread8(u8 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	return ioread8(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static inline u16 ifc_ioread16 (__le16 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	return ioread16(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static inline u32 ifc_ioread32(__le32 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static inline void ifc_iowrite8(u8 value, u8 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	iowrite8(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static inline void ifc_iowrite16(u16 value, __le16 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	iowrite16(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static inline void ifc_iowrite32(u32 value, __le32 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	iowrite32(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static void ifc_iowrite64_twopart(u64 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 				  __le32 __iomem *lo, __le32 __iomem *hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	ifc_iowrite32((u32)val, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	ifc_iowrite32(val >> 32, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct ifcvf_adapter *vf_to_adapter(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return container_of(hw, struct ifcvf_adapter, vf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static void __iomem *get_cap_addr(struct ifcvf_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 				  struct virtio_pci_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct ifcvf_adapter *ifcvf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 length, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u8 bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	length = le32_to_cpu(cap->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	offset = le32_to_cpu(cap->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	bar = cap->bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ifcvf= vf_to_adapter(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	pdev = ifcvf->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (bar >= IFCVF_PCI_MAX_RESOURCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		IFCVF_DBG(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			  "Invalid bar number %u to get capabilities\n", bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (offset + length > pci_resource_len(pdev, bar)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		IFCVF_DBG(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			  "offset(%u) + len(%u) overflows bar%u's capability\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			  offset, length, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return hw->base[bar] + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int ifcvf_read_config_range(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				   uint32_t *val, int size, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	for (i = 0; i < size; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		ret = pci_read_config_dword(dev, where + i, val + i / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) int ifcvf_init_hw(struct ifcvf_hw *hw, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct virtio_pci_cap cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u16 notify_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u8 pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		IFCVF_ERR(pdev, "Failed to read PCI capability list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	while (pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		ret = ifcvf_read_config_range(pdev, (u32 *)&cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 					      sizeof(cap), pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			IFCVF_ERR(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				  "Failed to get PCI capability at %x\n", pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (cap.cap_vndr != PCI_CAP_ID_VNDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		switch (cap.cfg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		case VIRTIO_PCI_CAP_COMMON_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			hw->common_cfg = get_cap_addr(hw, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			IFCVF_DBG(pdev, "hw->common_cfg = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				  hw->common_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		case VIRTIO_PCI_CAP_NOTIFY_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			pci_read_config_dword(pdev, pos + sizeof(cap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 					      &hw->notify_off_multiplier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			hw->notify_bar = cap.bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			hw->notify_base = get_cap_addr(hw, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			IFCVF_DBG(pdev, "hw->notify_base = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				  hw->notify_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		case VIRTIO_PCI_CAP_ISR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			hw->isr = get_cap_addr(hw, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			IFCVF_DBG(pdev, "hw->isr = %p\n", hw->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		case VIRTIO_PCI_CAP_DEVICE_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			hw->net_cfg = get_cap_addr(hw, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			IFCVF_DBG(pdev, "hw->net_cfg = %p\n", hw->net_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		pos = cap.cap_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (hw->common_cfg == NULL || hw->notify_base == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	    hw->isr == NULL || hw->net_cfg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		IFCVF_ERR(pdev, "Incomplete PCI capabilities\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	for (i = 0; i < IFCVF_MAX_QUEUE_PAIRS * 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		ifc_iowrite16(i, &hw->common_cfg->queue_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		notify_off = ifc_ioread16(&hw->common_cfg->queue_notify_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		hw->vring[i].notify_addr = hw->notify_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			notify_off * hw->notify_off_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	hw->lm_cfg = hw->base[IFCVF_LM_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	IFCVF_DBG(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		  "PCI capability mapping: common cfg: %p, notify base: %p\n, isr cfg: %p, device cfg: %p, multiplier: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		  hw->common_cfg, hw->notify_base, hw->isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		  hw->net_cfg, hw->notify_off_multiplier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 ifcvf_get_status(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return ifc_ioread8(&hw->common_cfg->device_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void ifcvf_set_status(struct ifcvf_hw *hw, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ifc_iowrite8(status, &hw->common_cfg->device_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void ifcvf_reset(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	hw->config_cb.callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	hw->config_cb.private = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ifcvf_set_status(hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* flush set_status, make sure VF is stopped, reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ifcvf_get_status(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void ifcvf_add_status(struct ifcvf_hw *hw, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		status |= ifcvf_get_status(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	ifcvf_set_status(hw, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ifcvf_get_status(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u64 ifcvf_get_features(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u32 features_lo, features_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ifc_iowrite32(0, &cfg->device_feature_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	features_lo = ifc_ioread32(&cfg->device_feature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ifc_iowrite32(1, &cfg->device_feature_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	features_hi = ifc_ioread32(&cfg->device_feature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return ((u64)features_hi << 32) | features_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void ifcvf_read_net_config(struct ifcvf_hw *hw, u64 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			   void *dst, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u8 old_gen, new_gen, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	WARN_ON(offset + length > sizeof(struct virtio_net_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		old_gen = ifc_ioread8(&hw->common_cfg->config_generation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		p = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		for (i = 0; i < length; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			*p++ = ifc_ioread8(hw->net_cfg + offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		new_gen = ifc_ioread8(&hw->common_cfg->config_generation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	} while (old_gen != new_gen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void ifcvf_write_net_config(struct ifcvf_hw *hw, u64 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			    const void *src, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	const u8 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	p = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	WARN_ON(offset + length > sizeof(struct virtio_net_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	for (i = 0; i < length; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		ifc_iowrite8(*p++, hw->net_cfg + offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void ifcvf_set_features(struct ifcvf_hw *hw, u64 features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ifc_iowrite32(0, &cfg->guest_feature_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ifc_iowrite32((u32)features, &cfg->guest_feature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ifc_iowrite32(1, &cfg->guest_feature_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ifc_iowrite32(features >> 32, &cfg->guest_feature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int ifcvf_config_features(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct ifcvf_adapter *ifcvf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ifcvf = vf_to_adapter(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ifcvf_set_features(hw, hw->req_features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ifcvf_add_status(hw, VIRTIO_CONFIG_S_FEATURES_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (!(ifcvf_get_status(hw) & VIRTIO_CONFIG_S_FEATURES_OK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		IFCVF_ERR(ifcvf->pdev, "Failed to set FEATURES_OK status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u16 ifcvf_get_vq_state(struct ifcvf_hw *hw, u16 qid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct ifcvf_lm_cfg __iomem *ifcvf_lm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	void __iomem *avail_idx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	u16 last_avail_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	u32 q_pair_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ifcvf_lm = (struct ifcvf_lm_cfg __iomem *)hw->lm_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	q_pair_id = qid / (IFCVF_MAX_QUEUE_PAIRS * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	avail_idx_addr = &ifcvf_lm->vring_lm_cfg[q_pair_id].idx_addr[qid % 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	last_avail_idx = ifc_ioread16(avail_idx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return last_avail_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int ifcvf_set_vq_state(struct ifcvf_hw *hw, u16 qid, u16 num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct ifcvf_lm_cfg __iomem *ifcvf_lm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	void __iomem *avail_idx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	u32 q_pair_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ifcvf_lm = (struct ifcvf_lm_cfg __iomem *)hw->lm_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	q_pair_id = qid / (IFCVF_MAX_QUEUE_PAIRS * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	avail_idx_addr = &ifcvf_lm->vring_lm_cfg[q_pair_id].idx_addr[qid % 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	hw->vring[qid].last_avail_idx = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	ifc_iowrite16(num, avail_idx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int ifcvf_hw_enable(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct virtio_pci_common_cfg __iomem *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct ifcvf_adapter *ifcvf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	ifcvf = vf_to_adapter(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	cfg = hw->common_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	ifc_iowrite16(IFCVF_MSI_CONFIG_OFF, &cfg->msix_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (ifc_ioread16(&cfg->msix_config) == VIRTIO_MSI_NO_VECTOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		IFCVF_ERR(ifcvf->pdev, "No msix vector for device config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	for (i = 0; i < hw->nr_vring; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		if (!hw->vring[i].ready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		ifc_iowrite16(i, &cfg->queue_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		ifc_iowrite64_twopart(hw->vring[i].desc, &cfg->queue_desc_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				     &cfg->queue_desc_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		ifc_iowrite64_twopart(hw->vring[i].avail, &cfg->queue_avail_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				      &cfg->queue_avail_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		ifc_iowrite64_twopart(hw->vring[i].used, &cfg->queue_used_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				     &cfg->queue_used_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		ifc_iowrite16(hw->vring[i].size, &cfg->queue_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		ifc_iowrite16(i + IFCVF_MSI_QUEUE_OFF, &cfg->queue_msix_vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		if (ifc_ioread16(&cfg->queue_msix_vector) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		    VIRTIO_MSI_NO_VECTOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			IFCVF_ERR(ifcvf->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				  "No msix vector for queue %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		ifcvf_set_vq_state(hw, i, hw->vring[i].last_avail_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		ifc_iowrite16(1, &cfg->queue_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void ifcvf_hw_disable(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct virtio_pci_common_cfg __iomem *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	cfg = hw->common_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	ifc_iowrite16(VIRTIO_MSI_NO_VECTOR, &cfg->msix_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	for (i = 0; i < hw->nr_vring; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		ifc_iowrite16(i, &cfg->queue_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		ifc_iowrite16(VIRTIO_MSI_NO_VECTOR, &cfg->queue_msix_vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	ifc_ioread16(&cfg->queue_msix_vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ifcvf_start_hw(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	ifcvf_reset(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	ifcvf_add_status(hw, VIRTIO_CONFIG_S_ACKNOWLEDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	ifcvf_add_status(hw, VIRTIO_CONFIG_S_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (ifcvf_config_features(hw) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (ifcvf_hw_enable(hw) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	ifcvf_add_status(hw, VIRTIO_CONFIG_S_DRIVER_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) void ifcvf_stop_hw(struct ifcvf_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ifcvf_hw_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	ifcvf_reset(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) void ifcvf_notify_queue(struct ifcvf_hw *hw, u16 qid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ifc_iowrite16(qid, hw->vring[qid].notify_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }