^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * USB ConnectTech WhiteHEAT driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Connect Tech Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1999, 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Greg Kroah-Hartman (greg@kroah.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * See Documentation/usb/usb-serial.rst for more information on using this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __LINUX_USB_SERIAL_WHITEHEAT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __LINUX_USB_SERIAL_WHITEHEAT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* WhiteHEAT commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WHITEHEAT_OPEN 1 /* open the port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WHITEHEAT_CLOSE 2 /* close the port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WHITEHEAT_SETUP_PORT 3 /* change port settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WHITEHEAT_SET_RTS 4 /* turn RTS on or off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WHITEHEAT_SET_DTR 5 /* turn DTR on or off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WHITEHEAT_SET_BREAK 6 /* turn BREAK on or off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WHITEHEAT_DUMP 7 /* dump memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WHITEHEAT_STATUS 8 /* get status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WHITEHEAT_PURGE 9 /* clear the UART fifos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WHITEHEAT_GET_DTR_RTS 10 /* get the state of DTR and RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) for a port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WHITEHEAT_GET_HW_INFO 11 /* get EEPROM info and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) hardware ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WHITEHEAT_REPORT_TX_DONE 12 /* get the next TX done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WHITEHEAT_EVENT 13 /* unsolicited status events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WHITEHEAT_ECHO 14 /* send data to the indicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) IN endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WHITEHEAT_DO_TEST 15 /* perform specified test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WHITEHEAT_CMD_COMPLETE 16 /* reply for some commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WHITEHEAT_CMD_FAILURE 17 /* reply for failed commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Commands to the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * WHITEHEAT_OPEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * WHITEHEAT_CLOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * WHITEHEAT_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * WHITEHEAT_GET_DTR_RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * WHITEHEAT_REPORT_TX_DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct whiteheat_simple {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __u8 port; /* port number (1 to N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * WHITEHEAT_SETUP_PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WHITEHEAT_PAR_NONE 'n' /* no parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WHITEHEAT_PAR_EVEN 'e' /* even parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WHITEHEAT_PAR_ODD 'o' /* odd parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WHITEHEAT_PAR_SPACE '0' /* space (force 0) parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WHITEHEAT_PAR_MARK '1' /* mark (force 1) parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WHITEHEAT_SFLOW_NONE 'n' /* no software flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WHITEHEAT_SFLOW_RX 'r' /* XOFF/ON is sent when RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) fills/empties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WHITEHEAT_SFLOW_TX 't' /* when received XOFF/ON will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) stop/start TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WHITEHEAT_SFLOW_RXTX 'b' /* both SFLOW_RX and SFLOW_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WHITEHEAT_HFLOW_NONE 0x00 /* no hardware flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WHITEHEAT_HFLOW_RTS_TOGGLE 0x01 /* RTS is on during transmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) off otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define WHITEHEAT_HFLOW_DTR 0x02 /* DTR is off/on when RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) fills/empties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define WHITEHEAT_HFLOW_CTS 0x08 /* when received CTS off/on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) will stop/start TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WHITEHEAT_HFLOW_DSR 0x10 /* when received DSR off/on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) will stop/start TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WHITEHEAT_HFLOW_RTS 0x80 /* RTS is off/on when RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) fills/empties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct whiteheat_port_settings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __u8 port; /* port number (1 to N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __le32 baud; /* any value 7 - 460800, firmware calculates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) best fit; arrives little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __u8 bits; /* 5, 6, 7, or 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __u8 stop; /* 1 or 2, default 1 (2 = 1.5 if bits = 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __u8 parity; /* see WHITEHEAT_PAR_* above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __u8 sflow; /* see WHITEHEAT_SFLOW_* above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __u8 xoff; /* XOFF byte value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __u8 xon; /* XON byte value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __u8 hflow; /* see WHITEHEAT_HFLOW_* above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __u8 lloop; /* 0/1 turns local loopback mode off/on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * WHITEHEAT_SET_RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * WHITEHEAT_SET_DTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * WHITEHEAT_SET_BREAK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WHITEHEAT_RTS_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WHITEHEAT_RTS_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WHITEHEAT_DTR_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WHITEHEAT_DTR_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WHITEHEAT_BREAK_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WHITEHEAT_BREAK_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct whiteheat_set_rdb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __u8 port; /* port number (1 to N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __u8 state; /* 0/1 turns signal off/on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * WHITEHEAT_DUMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WHITEHEAT_DUMP_MEM_DATA 'd' /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define WHITEHEAT_DUMP_MEM_IDATA 'i' /* idata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define WHITEHEAT_DUMP_MEM_BDATA 'b' /* bdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define WHITEHEAT_DUMP_MEM_XDATA 'x' /* xdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Allowable address ranges (firmware checks address):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Type DATA: 0x00 - 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Type IDATA: 0x80 - 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Type BDATA: 0x20 - 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Type XDATA: 0x0000 - 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * B/I/DATA all read the local memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * XDATA reads the external memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * BDATA returns bits as bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * NOTE: 0x80 - 0xff (local space) are the Special Function Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * of the 8051, and some have on-read side-effects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct whiteheat_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __u8 mem_type; /* see WHITEHEAT_DUMP_* above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __u16 addr; /* address, see restrictions above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __u16 length; /* number of bytes to dump, max 63 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * WHITEHEAT_PURGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define WHITEHEAT_PURGE_RX 0x01 /* purge rx fifos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define WHITEHEAT_PURGE_TX 0x02 /* purge tx fifos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct whiteheat_purge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) __u8 port; /* port number (1 to N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __u8 what; /* bit pattern of what to purge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * WHITEHEAT_ECHO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct whiteheat_echo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) __u8 port; /* port number (1 to N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __u8 length; /* length of message to echo, max 61 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __u8 echo_data[61]; /* data to echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * WHITEHEAT_DO_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define WHITEHEAT_TEST_UART_RW 0x01 /* read/write uart registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define WHITEHEAT_TEST_UART_INTR 0x02 /* uart interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define WHITEHEAT_TEST_SETUP_CONT 0x03 /* setup for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PORT_CONT/PORT_DISCONT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define WHITEHEAT_TEST_PORT_CONT 0x04 /* port connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define WHITEHEAT_TEST_PORT_DISCONT 0x05 /* port disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define WHITEHEAT_TEST_UART_CLK_START 0x06 /* uart clock test start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define WHITEHEAT_TEST_UART_CLK_STOP 0x07 /* uart clock test stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define WHITEHEAT_TEST_MODEM_FT 0x08 /* modem signals, requires a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) loopback cable/connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define WHITEHEAT_TEST_ERASE_EEPROM 0x09 /* erase eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define WHITEHEAT_TEST_READ_EEPROM 0x0a /* read eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define WHITEHEAT_TEST_PROGRAM_EEPROM 0x0b /* program eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct whiteheat_test {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __u8 port; /* port number (1 to n) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __u8 test; /* see WHITEHEAT_TEST_* above*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __u8 info[32]; /* additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Replies from the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * WHITEHEAT_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define WHITEHEAT_EVENT_MODEM 0x01 /* modem field is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define WHITEHEAT_EVENT_ERROR 0x02 /* error field is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define WHITEHEAT_EVENT_FLOW 0x04 /* flow field is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define WHITEHEAT_EVENT_CONNECT 0x08 /* connect field is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define WHITEHEAT_FLOW_NONE 0x00 /* no flow control active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define WHITEHEAT_FLOW_HARD_OUT 0x01 /* TX is stopped by CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (waiting for CTS to go on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define WHITEHEAT_FLOW_HARD_IN 0x02 /* remote TX is stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) by RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define WHITEHEAT_FLOW_SOFT_OUT 0x04 /* TX is stopped by XOFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) received (waiting for XON) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define WHITEHEAT_FLOW_SOFT_IN 0x08 /* remote TX is stopped by XOFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define WHITEHEAT_FLOW_TX_DONE 0x80 /* TX has completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct whiteheat_status_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __u8 port; /* port number (1 to N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __u8 event; /* indicates what the current event is,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) see WHITEHEAT_EVENT_* above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __u8 modem; /* modem signal status (copy of uart's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MSR register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __u8 error; /* line status (copy of uart's LSR register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __u8 flow; /* flow control state, see WHITEHEAT_FLOW_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __u8 connect; /* 0 means not connected, non-zero means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * WHITEHEAT_GET_DTR_RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct whiteheat_dr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __u8 mcr; /* copy of uart's MCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * WHITEHEAT_GET_HW_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct whiteheat_hw_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __u8 hw_id; /* hardware id number, WhiteHEAT = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __u8 sw_major_rev; /* major version number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __u8 sw_minor_rev; /* minor version number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct whiteheat_hw_eeprom_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __u8 b0; /* B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __u8 vendor_id_low; /* vendor id (low byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __u8 vendor_id_high; /* vendor id (high byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __u8 product_id_low; /* product id (low byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) __u8 product_id_high; /* product id (high byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __u8 device_id_low; /* device id (low byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __u8 device_id_high; /* device id (high byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __u8 not_used_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __u8 serial_number_0; /* serial number (low byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __u8 serial_number_1; /* serial number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __u8 serial_number_2; /* serial number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __u8 serial_number_3; /* serial number (high byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __u8 not_used_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __u8 not_used_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __u8 checksum_low; /* checksum (low byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __u8 checksum_high; /* checksum (high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } hw_eeprom_info; /* EEPROM contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * WHITEHEAT_EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct whiteheat_event_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __u8 port; /* port number (1 to N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __u8 event; /* see whiteheat_status_info.event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __u8 info; /* see whiteheat_status_info.modem, .error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .flow, .connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * WHITEHEAT_DO_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define WHITEHEAT_TEST_FAIL 0x00 /* test failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define WHITEHEAT_TEST_UNKNOWN 0x01 /* unknown test requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define WHITEHEAT_TEST_PASS 0xff /* test passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct whiteheat_test_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __u8 port; /* port number (1 to N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __u8 test; /* indicates which test this is a response for,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) see WHITEHEAT_DO_TEST above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) __u8 status; /* see WHITEHEAT_TEST_* above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __u8 results[32]; /* test-dependent results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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