^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Definitions for MCT (Magic Control Technology) USB-RS232 Converter Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2000 Wolfgang Grandegger (wolfgang@ces.ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver is for the device MCT USB-RS232 Converter (25 pin, Model No.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * U232-P25) from Magic Control Technology Corp. (there is also a 9 pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Model No. U232-P9). See http://www.mct.com.tw/products/product_us232.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * for further information. The properties of this device are listed at the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * of this file. This device was used in the Dlink DSB-S25.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * All of the information about the device was acquired by using SniffUSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * on Windows98. The technical details of the reverse engineering are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * summarized at the end of this file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __LINUX_USB_SERIAL_MCT_U232_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __LINUX_USB_SERIAL_MCT_U232_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MCT_U232_VID 0x0711 /* Vendor Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MCT_U232_PID 0x0210 /* Original MCT Product Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* U232-P25, Sitecom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCT_U232_SITECOM_PID 0x0230 /* Sitecom Product Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* DU-H3SP USB BAY hub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCT_U232_DU_H3SP_PID 0x0200 /* D-Link DU-H3SP USB BAY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Belkin badge the MCT U232-P9 as the F5U109 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCT_U232_BELKIN_F5U109_VID 0x050d /* Vendor Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCT_U232_BELKIN_F5U109_PID 0x0109 /* Product Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Vendor Request Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCT_U232_SET_REQUEST_TYPE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCT_U232_GET_REQUEST_TYPE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Get Modem Status Register (MSR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCT_U232_GET_MODEM_STAT_REQUEST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCT_U232_GET_MODEM_STAT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Get Line Control Register (LCR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* ... not used by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCT_U232_GET_LINE_CTRL_REQUEST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCT_U232_GET_LINE_CTRL_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Set Baud Rate Divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCT_U232_SET_BAUD_RATE_REQUEST 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCT_U232_SET_BAUD_RATE_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Set Line Control Register (LCR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCT_U232_SET_LINE_CTRL_REQUEST 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCT_U232_SET_LINE_CTRL_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Set Modem Control Register (MCR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCT_U232_SET_MODEM_CTRL_REQUEST 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCT_U232_SET_MODEM_CTRL_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * This USB device request code is not well understood. It is transmitted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * the MCT-supplied Windows driver whenever the baud rate changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCT_U232_SET_UNKNOWN1_REQUEST 11 /* Unknown functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCT_U232_SET_UNKNOWN1_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * This USB device request code appears to control whether CTS is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * during transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Sending a zero byte allows data transmission to a device which is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * asserting CTS. Sending a '1' byte will cause transmission to be deferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * until the device asserts CTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MCT_U232_SET_CTS_REQUEST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MCT_U232_SET_CTS_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCT_U232_MAX_SIZE 4 /* of MCT_XXX_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Baud rate (divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Actually, there are two of them, MCT website calls them "Philips solution"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * and "Intel solution". They are the regular MCT and "Sitecom" for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * This is pointless to document in the header, see the code for the bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int mct_u232_calculate_baud_rate(struct usb_serial *serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) speed_t value, speed_t *result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Line Control Register (LCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MCT_U232_SET_BREAK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MCT_U232_PARITY_SPACE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MCT_U232_PARITY_MARK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MCT_U232_PARITY_EVEN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MCT_U232_PARITY_ODD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MCT_U232_PARITY_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCT_U232_DATA_BITS_5 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MCT_U232_DATA_BITS_6 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCT_U232_DATA_BITS_7 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCT_U232_DATA_BITS_8 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCT_U232_STOP_BITS_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCT_U232_STOP_BITS_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Modem Control Register (MCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MCT_U232_MCR_NONE 0x8 /* Deactivate DTR and RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCT_U232_MCR_RTS 0xa /* Activate RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCT_U232_MCR_DTR 0x9 /* Activate DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Modem Status Register (MSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCT_U232_MSR_INDEX 0x0 /* data[index] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCT_U232_MSR_CD 0x80 /* Current CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCT_U232_MSR_RI 0x40 /* Current RI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MCT_U232_MSR_DSR 0x20 /* Current DSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCT_U232_MSR_CTS 0x10 /* Current CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCT_U232_MSR_DCD 0x08 /* Delta CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCT_U232_MSR_DRI 0x04 /* Delta RI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCT_U232_MSR_DDSR 0x02 /* Delta DSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCT_U232_MSR_DCTS 0x01 /* Delta CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Line Status Register (LSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCT_U232_LSR_INDEX 1 /* data[index] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCT_U232_LSR_ERR 0x80 /* OE | PE | FE | BI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCT_U232_LSR_TEMT 0x40 /* transmit register empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCT_U232_LSR_THRE 0x20 /* transmit holding register empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCT_U232_LSR_BI 0x10 /* break indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCT_U232_LSR_FE 0x08 /* framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCT_U232_LSR_OE 0x02 /* overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCT_U232_LSR_PE 0x04 /* parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCT_U232_LSR_OE 0x02 /* overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MCT_U232_LSR_DR 0x01 /* receive data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Technical Specification reverse engineered with SniffUSB on Windows98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * =====================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * The technical details of the device have been acquired be using "SniffUSB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * and the vendor-supplied device driver (version 2.3A) under Windows98. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * identify the USB vendor-specific requests and to assign them to terminal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * settings (flow control, baud rate, etc.) the program "SerialSettings" from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * William G. Greathouse has been proven to be very useful. I also used the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Win98 "HyperTerminal" and "usb-robot" on Linux for testing. The results and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * observations are summarized below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * The USB requests seem to be directly mapped to the registers of a 8250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * 16450 or 16550 UART. The FreeBSD handbook (appendix F.4 "Input/Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * devices") contains a comprehensive description of UARTs and its registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * The bit descriptions are actually taken from there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Baud rate (divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * BmRequestType: 0x40 (0100 0000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * bRequest: 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * wValue: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * wIndex: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * wLength: 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Data: divisor = 115200 / baud_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * SniffUSB observations (Nov 2003): Contrary to the 'wLength' value of 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * shown above, observations with a Belkin F5U109 adapter, using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * MCT-supplied Windows98 driver (U2SPORT.VXD, "File version: 1.21P.0104 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Win98/Me"), show this request has a length of 1 byte, presumably because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * of the fact that the Belkin adapter and the 'Sitecom U232-P25' adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * use a baud-rate code instead of a conventional RS-232 baud rate divisor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * The current source code for this driver does not reflect this fact, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * the driver works fine with this adapter/driver combination nonetheless.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Line Control Register (LCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * BmRequestType: 0x40 (0100 0000B) 0xc0 (1100 0000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * bRequest: 0x07 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * wValue: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * wIndex: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * wLength: 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Data: LCR (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Bit 7: Divisor Latch Access Bit (DLAB). When set, access to the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * transmit/receive register (THR/RBR) and the Interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * (IER) is disabled. Any access to these ports is now redirected to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Divisor Latch Registers. Setting this bit, loading the Divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Registers, and clearing DLAB should be done with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Bit 6: Set Break. When set to "1", the transmitter begins to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * continuous Spacing until this bit is set to "0". This overrides any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * bits of characters that are being transmitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Bit 5: Stick Parity. When parity is enabled, setting this bit causes parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * to always be "1" or "0", based on the value of Bit 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Bit 4: Even Parity Select (EPS). When parity is enabled and Bit 5 is "0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * setting this bit causes even parity to be transmitted and expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Otherwise, odd parity is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Bit 3: Parity Enable (PEN). When set to "1", a parity bit is inserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * between the last bit of the data and the Stop Bit. The UART will also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * expect parity to be present in the received data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Bit 2: Number of Stop Bits (STB). If set to "1" and using 5-bit data words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * 1.5 Stop Bits are transmitted and expected in each data word. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * 6, 7 and 8-bit data words, 2 Stop Bits are transmitted and expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * When this bit is set to "0", one Stop Bit is used on each data word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Bit 1: Word Length Select Bit #1 (WLSB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Bit 0: Word Length Select Bit #0 (WLSB0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Together these bits specify the number of bits in each data word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * 1 0 Word Length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * 0 0 5 Data Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * 0 1 6 Data Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * 1 0 7 Data Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * 1 1 8 Data Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * SniffUSB observations: Bit 7 seems not to be used. There seem to be two bugs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * in the Win98 driver: the break does not work (bit 6 is not asserted) and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * stick parity bit is not cleared when set once. The LCR can also be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * back with USB request 6 but this has never been observed with SniffUSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Modem Control Register (MCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * ----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * BmRequestType: 0x40 (0100 0000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * bRequest: 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * wValue: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * wIndex: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * wLength: 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Data: MCR (Bit 4..7, see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Bit 7: Reserved, always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Bit 6: Reserved, always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Bit 5: Reserved, always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Bit 4: Loop-Back Enable. When set to "1", the UART transmitter and receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * are internally connected together to allow diagnostic operations. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * addition, the UART modem control outputs are connected to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * modem control inputs. CTS is connected to RTS, DTR is connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * DSR, OUT1 is connected to RI, and OUT 2 is connected to DCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Bit 3: OUT 2. An auxiliary output that the host processor may set high or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * low. In the IBM PC serial adapter (and most clones), OUT 2 is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * to tri-state (disable) the interrupt signal from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * 8250/16450/16550 UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Bit 2: OUT 1. An auxiliary output that the host processor may set high or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * low. This output is not used on the IBM PC serial adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Bit 1: Request to Send (RTS). When set to "1", the output of the UART -RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * line is Low (Active).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * -DTR line is Low (Active).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * SniffUSB observations: Bit 2 and 4 seem not to be used but bit 3 has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * seen _always_ set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Modem Status Register (MSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * BmRequestType: 0xc0 (1100 0000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * bRequest: 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * wValue: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * wIndex: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * wLength: 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Data: MSR (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Bit 7: Data Carrier Detect (CD). Reflects the state of the DCD line on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Bit 6: Ring Indicator (RI). Reflects the state of the RI line on the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Bit 5: Data Set Ready (DSR). Reflects the state of the DSR line on the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Bit 4: Clear To Send (CTS). Reflects the state of the CTS line on the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Bit 3: Delta Data Carrier Detect (DDCD). Set to "1" if the -DCD line has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * changed state one more more times since the last time the MSR was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * read by the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Bit 2: Trailing Edge Ring Indicator (TERI). Set to "1" if the -RI line has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * had a low to high transition since the last time the MSR was read by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Bit 1: Delta Data Set Ready (DDSR). Set to "1" if the -DSR line has changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * state one more more times since the last time the MSR was read by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Bit 0: Delta Clear To Send (DCTS). Set to "1" if the -CTS line has changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * state one more times since the last time the MSR was read by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * SniffUSB observations: the MSR is also returned as first byte on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * interrupt-in endpoint 0x83 to signal changes of modem status lines. The USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * request to read MSR cannot be applied during normal device operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Line Status Register (LSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * --------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Bit 7 Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * This bit is set to "1" when any of the bytes in the FIFO have one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * or more of the following error conditions: PE, FE, or BI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Bit 6 Transmitter Empty (TEMT). When set to "1", there are no words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * remaining in the transmit FIFO or the transmit shift register. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * transmitter is completely idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Bit 5 Transmitter Holding Register Empty (THRE). When set to "1", the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * FIFO (or holding register) now has room for at least one additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * word to transmit. The transmitter may still be transmitting when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * this bit is set to "1".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Bit 4 Break Interrupt (BI). The receiver has detected a Break signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Bit 3 Framing Error (FE). A Start Bit was detected but the Stop Bit did
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * not appear at the expected time. The received word is probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * garbled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Bit 2 Parity Error (PE). The parity bit was incorrect for the word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Bit 1 Overrun Error (OE). A new word was received and there was no room
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * in the receive buffer. The newly-arrived word in the shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * is discarded. On 8250/16450 UARTs, the word in the holding register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * is discarded and the newly- arrived word is put in the holding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Bit 0 Data Ready (DR). One or more words are in the receive FIFO that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * host may read. A word must be completely received and moved from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * the shift register into the FIFO (or holding register for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * 8250/16450 designs) before this bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * SniffUSB observations: the LSR is returned as second byte on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * interrupt-in endpoint 0x83 to signal error conditions. Such errors have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * been seen with minicom/zmodem transfers (CRC errors).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Unknown #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * BmRequestType: 0x40 (0100 0000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * bRequest: 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * wValue: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * wIndex: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * wLength: 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Data: 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * SniffUSB observations (Nov 2003): With the MCT-supplied Windows98 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * (U2SPORT.VXD, "File version: 1.21P.0104 for Win98/Me"), this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * occurs immediately after a "Baud rate (divisor)" message. It was not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * observed at any other time. It is unclear what purpose this message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * serves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Unknown #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * BmRequestType: 0x40 (0100 0000B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * bRequest: 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * wValue: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * wIndex: 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * wLength: 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Data: 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * SniffUSB observations (Nov 2003): With the MCT-supplied Windows98 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * (U2SPORT.VXD, "File version: 1.21P.0104 for Win98/Me"), this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * occurs immediately after the 'Unknown #1' message (see above). It was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * not observed at any other time. It is unclear what other purpose (if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * any) this message might serve, but without it, the USB/RS-232 adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * will not write to RS-232 devices which do not assert the 'CTS' signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * SniffUSB observations: no flow control specific requests have been realized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * apart from DTR/RTS settings. Both signals are dropped for no flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * but asserted for hardware or software flow control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Endpoint usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * SniffUSB observations: the bulk-out endpoint 0x1 and interrupt-in endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * 0x81 is used to transmit and receive characters. The second interrupt-in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * endpoint 0x83 signals exceptional conditions like modem line changes and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * errors. The first byte returned is the MSR and the second byte the LSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Other observations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * ------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Queued bulk transfers like used in visor.c did not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Properties of the USB device used (as found in /var/log/messages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * -----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Manufacturer: MCT Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * Product: USB-232 Interfact Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * SerialNumber: U2S22050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Length = 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * DescriptorType = 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * USB version = 1.00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Vendor:Product = 0711:0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * MaxPacketSize0 = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * NumConfigurations = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Device version = 1.02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Device Class:SubClass:Protocol = 00:00:00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Per-interface classes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * bLength = 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * bDescriptorType = 02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * wTotalLength = 0027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * bNumInterfaces = 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * bConfigurationValue = 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * iConfiguration = 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * bmAttributes = c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * MaxPower = 100mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Interface: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Alternate Setting: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * bLength = 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * bDescriptorType = 04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * bInterfaceNumber = 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * bAlternateSetting = 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * bNumEndpoints = 03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * bInterface Class:SubClass:Protocol = 00:00:00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * iInterface = 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * Endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * bLength = 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * bDescriptorType = 05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * bEndpointAddress = 81 (in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * bmAttributes = 03 (Interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * wMaxPacketSize = 0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * bInterval = 02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * bLength = 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * bDescriptorType = 05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * bEndpointAddress = 01 (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * bmAttributes = 02 (Bulk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * wMaxPacketSize = 0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * bInterval = 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * bLength = 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * bDescriptorType = 05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * bEndpointAddress = 83 (in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * bmAttributes = 03 (Interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * wMaxPacketSize = 0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * bInterval = 02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Hardware details (added by Martin Hamilton, 2001/12/06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * -----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * This info was gleaned from opening a Belkin F5U109 DB9 USB serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * adaptor, which turns out to simply be a re-badged U232-P9. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * know this because there is a sticky label on the circuit board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * which says "U232-P9" ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * The circuit board inside the adaptor contains a Philips PDIUSBD12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * USB endpoint chip and a Philips P87C52UBAA microcontroller with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * embedded UART. Exhaustive documentation for these is available at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * http://www.semiconductors.philips.com/pip/p87c52ubaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * http://www.nxp.com/acrobat_download/various/PDIUSBD12_PROGRAMMING_GUIDE.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Thanks to Julian Highfield for the pointer to the Philips database.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #endif /* __LINUX_USB_SERIAL_MCT_U232_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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