Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 	usa90msg.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 	Copyright (c) 1998-2003 InnoSys Incorporated.  All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	This file is available under a BSD-style copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 	Keyspan USB Async Message Formats for the USA19HS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	modification, are permitted provided that the following conditions are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	1. Redistributions of source code must retain this licence text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)    	without modification, this list of conditions, and the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)    	disclaimer.  The following copyright notice must appear immediately at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)    	the beginning of all source files:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)         	Copyright (c) 1998-2003 InnoSys Incorporated.  All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)         	This file is available under a BSD-style copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	2. The name of InnoSys Incorporated may not be used to endorse or promote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)    	products derived from this software without specific prior written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)    	permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	THIS SOFTWARE IS PROVIDED BY INNOSYS CORP. ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	SUCH DAMAGE.    
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	Revisions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	2003feb14		add setTxMode/txMode  and cancelRxXoff to portControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	2003mar21		change name of PARITY_0/1 to add MARK/SPACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #ifndef	__USA90MSG__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	__USA90MSG__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct keyspan_usa90_portControlMessage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		there are three types of "commands" sent in the control message:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		1.	configuration changes which must be requested by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			the corresponding "set" flag (and should only be requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			when necessary, to reduce overhead on the device):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u8	setClocking,	// host requests baud rate be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		baudLo,			// host does baud divisor calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		baudHi,			// host does baud divisor calculation 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		setLcr,			// host requests lcr be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		lcr,			// use PARITY, STOPBITS, DATABITS below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		setRxMode,		// set receive mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		rxMode,			// RXMODE_DMA or RXMODE_BYHAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		setTxMode,		// set transmit mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		txMode,			// TXMODE_DMA or TXMODE_BYHAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		setTxFlowControl,	// host requests tx flow control be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		txFlowControl	,	// use TX_FLOW... bits below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		setRxFlowControl,	// host requests rx flow control be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		rxFlowControl,	// use RX_FLOW... bits below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		sendXoff,		// host requests XOFF transmitted immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		sendXon,		// host requests XON char transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		xonChar,		// specified in current character format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		xoffChar,		// specified in current character format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		sendChar,		// host requests char transmitted immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		txChar,			// character to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		setRts,			// host requests RTS output be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		rts,			// 1=on, 0=off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		setDtr, 		// host requests DTR output be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		dtr;			// 1=on, 0=off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		2.	configuration data which is simply used as is 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			and must be specified correctly in every host message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u8	rxForwardingLength,  // forward when this number of chars available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		rxForwardingTimeout, // (1-31 in ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		txAckSetting;	   // 0=don't ack, 1=normal, 2-255 TBD...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		3.	Firmware states which cause actions if they change					
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		and must be specified correctly in every host message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u8	portEnabled,	// 0=disabled, 1=enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		txFlush,		// 0=normal, 1=toss outbound data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		txBreak,		// 0=break off, 1=break on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		loopbackMode;	// 0=no loopback, 1=loopback enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		4.	commands which are flags only; these are processed in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			(so that, e.g., if rxFlush and rxForward flags are set, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			port will have no data to forward); any non-zero value 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			is respected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u8	rxFlush,		// toss inbound data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		rxForward,		// forward all inbound data, NOW (as if fwdLen==1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		cancelRxXoff,	// cancel any receive XOFF state (_txXoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		returnStatus;	// return current status NOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) // defines for bits in lcr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define		USA_DATABITS_5		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define		USA_DATABITS_6		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define		USA_DATABITS_7		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define		USA_DATABITS_8		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define		STOPBITS_5678_1		0x00	// 1 stop bit for all byte sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define		STOPBITS_5_1p5		0x04	// 1.5 stop bits for 5-bit byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define		STOPBITS_678_2		0x04	// 2 stop bits for 6-8 bit byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define		USA_PARITY_NONE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define		USA_PARITY_ODD		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define		USA_PARITY_EVEN		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define		PARITY_MARK_1  		0x28   	// force parity MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define		PARITY_SPACE_0 		0x38	// force parity SPACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define		TXFLOW_CTS			0x04	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define		TXFLOW_DSR			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define		TXFLOW_XOFF			0x01	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define		TXFLOW_XOFF_ANY		0x02	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define		TXFLOW_XOFF_BITS	(TXFLOW_XOFF | TXFLOW_XOFF_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define		RXFLOW_XOFF			0x10	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define		RXFLOW_RTS			0x20	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define		RXFLOW_DTR			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define		RXFLOW_DSR_SENSITIVITY	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define		RXMODE_BYHAND		0x00	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define		RXMODE_DMA			0x02	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define		TXMODE_BYHAND		0x00	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define		TXMODE_DMA			0x02	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) // all things called "StatusMessage" are sent on the status endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct keyspan_usa90_portStatusMessage	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u8	msr,			// reports the actual MSR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		cts,			// reports CTS pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dcd,			// reports DCD pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		dsr,			// reports DSR pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		ri,				// reports RI pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		_txXoff,		// port is in XOFF state (we received XOFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		rxBreak,		// reports break state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		rxOverrun,		// count of overrun errors (since last reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		rxParity,		// count of parity errors (since last reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		rxFrame,		// count of frame errors (since last reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		portState,		// PORTSTATE_xxx bits (useful for debugging)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		messageAck,		// message acknowledgement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		charAck,		// character acknowledgement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		controlResponse;	// (value = returnStatus) a control message has been processed 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) // bits in RX data message when STAT byte is included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define	RXERROR_OVERRUN		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define	RXERROR_PARITY		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define	RXERROR_FRAMING		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define	RXERROR_BREAK		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define	PORTSTATE_ENABLED	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define	PORTSTATE_TXFLUSH	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define	PORTSTATE_TXBREAK	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define	PORTSTATE_LOOPBACK 	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) // MSR bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define USA_MSR_dCTS	  		0x01		// CTS has changed since last report	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define USA_MSR_dDSR	  		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define USA_MSR_dRI			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define USA_MSR_dDCD	  		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define USA_MSR_CTS			0x10	  	// current state of CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define USA_MSR_DSR			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define USA_USA_MSR_RI			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MSR_DCD				0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) // ie: the maximum length of an endpoint buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define		MAX_DATA_LEN			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif