^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Infinity Unlimited USB Phoenix driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Alain Degreffe (eczema@ecze.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Original code taken from iuutool ( Copyright (C) 2006 Juan Carlos Borrás )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * And tested with help of WB Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IUU_USB_VENDOR_ID 0x104f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IUU_USB_PRODUCT_ID 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IUU_USB_OP_TIMEOUT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Programmer commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IUU_NO_OPERATION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IUU_GET_FIRMWARE_VERSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IUU_GET_PRODUCT_NAME 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IUU_GET_STATE_REGISTER 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IUU_SET_LED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IUU_WAIT_MUS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IUU_WAIT_MS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IUU_GET_LOADER_VERSION 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IUU_RST_SET 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IUU_RST_CLEAR 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IUU_SET_VCC 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IUU_UART_ENABLE 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IUU_UART_DISABLE 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IUU_UART_WRITE_I2C 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IUU_UART_ESC 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IUU_UART_TRAP 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IUU_UART_TRAP_BREAK 0x5B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IUU_UART_RX 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IUU_AVR_ON 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IUU_AVR_OFF 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IUU_AVR_1CLK 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IUU_AVR_RESET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IUU_AVR_RESET_PC 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IUU_AVR_INC_PC 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IUU_AVR_INCN_PC 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IUU_AVR_PREAD 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IUU_AVR_PREADN 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IUU_AVR_PWRITE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IUU_AVR_DREAD 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IUU_AVR_DREADN 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IUU_AVR_DWRITE 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IUU_AVR_PWRITEN 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IUU_EEPROM_ON 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IUU_EEPROM_OFF 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IUU_EEPROM_WRITE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IUU_EEPROM_WRITEX 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IUU_EEPROM_WRITE8 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IUU_EEPROM_WRITE16 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IUU_EEPROM_WRITEX32 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IUU_EEPROM_WRITEX64 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IUU_EEPROM_READ 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IUU_EEPROM_READX 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IUU_EEPROM_BREAD 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IUU_EEPROM_BREADX 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IUU_PIC_CMD 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IUU_PIC_CMD_LOAD 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IUU_PIC_CMD_READ 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IUU_PIC_ON 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IUU_PIC_OFF 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IUU_PIC_RESET 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IUU_PIC_INC_PC 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IUU_PIC_INCN_PC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IUU_PIC_PWRITE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IUU_PIC_PREAD 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IUU_PIC_PREADN 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IUU_PIC_DWRITE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IUU_PIC_DREAD 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IUU_UART_NOP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IUU_UART_CHANGE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IUU_UART_TX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IUU_DELAY_MS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IUU_OPERATION_OK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IUU_DEVICE_NOT_FOUND 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IUU_INVALID_HANDLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IUU_INVALID_PARAMETER 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IUU_INVALID_voidERFACE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IUU_INVALID_REQUEST_LENGTH 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IUU_UART_NOT_ENABLED 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IUU_WRITE_ERROR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IUU_READ_ERROR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IUU_TX_ERROR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IUU_RX_ERROR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IUU_PARITY_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IUU_PARITY_EVEN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IUU_PARITY_ODD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IUU_PARITY_MARK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IUU_PARITY_SPACE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IUU_SC_INSERTED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IUU_VERIFY_ERROR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IUU_SIM_INSERTED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IUU_TWO_STOP_BITS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IUU_ONE_STOP_BIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IUU_BAUD_2400 0x0398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IUU_BAUD_9600 0x0298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IUU_BAUD_19200 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IUU_BAUD_28800 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IUU_BAUD_38400 0x01B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IUU_BAUD_57600 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IUU_BAUD_115200 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IUU_CLK_3579000 3579000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IUU_CLK_3680000 3680000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IUU_CLK_6000000 6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IUU_FULLCARD_IN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IUU_DEV_ERROR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IUU_MINICARD_IN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IUU_VCC_5V 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IUU_VCC_3V 0x01
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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