^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1997-2002 Inside Out Networks, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Feb-16-2001 DMI Added I2C structure definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * May-29-2002 gkh Ported to Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _IO_TI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _IO_TI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DTK_ADDR_SPACE_XDATA 0x03 /* Addr is placed in XDATA space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* UART Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Bits per character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UMP_UART_CHAR5BITS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UMP_UART_CHAR6BITS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UMP_UART_CHAR7BITS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UMP_UART_CHAR8BITS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UMP_UART_NOPARITY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UMP_UART_ODDPARITY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UMP_UART_EVENPARITY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UMP_UART_MARKPARITY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UMP_UART_SPACEPARITY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UMP_UART_STOPBIT1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UMP_UART_STOPBIT15 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UMP_UART_STOPBIT2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Line status register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UMP_UART_LSR_OV_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UMP_UART_LSR_PE_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UMP_UART_LSR_FE_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UMP_UART_LSR_BR_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UMP_UART_LSR_ER_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UMP_UART_LSR_RX_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UMP_UART_LSR_TX_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UMP_UART_LSR_DATA_MASK (LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Port Settings Constants) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UMP_MASK_UART_FLAGS_RTS_DISABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UMP_MASK_UART_FLAGS_PARITY 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UMP_MASK_UART_FLAGS_OUT_X 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UMP_MASK_UART_FLAGS_OUT_XA 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UMP_MASK_UART_FLAGS_IN_X 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UMP_MASK_UART_FLAGS_DTR_FLOW 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UMP_MASK_UART_FLAGS_DTR_DISABLE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UMP_MASK_UART_FLAGS_RECEIVE_MS_INT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UMP_DMA_MODE_CONTINOUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UMP_PIPE_TRANS_TIMEOUT_ENA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UMP_PIPE_TRANSFER_MODE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define UMP_PIPE_TRANS_TIMEOUT_MASK 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Purge port Direction Mask Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UMP_PORT_DIR_OUT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define UMP_PORT_DIR_IN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Address of Port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define UMPM_UART1_PORT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UMPC_SET_CONFIG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define UMPC_OPEN_PORT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UMPC_CLOSE_PORT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UMPC_START_PORT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UMPC_STOP_PORT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UMPC_TEST_PORT 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UMPC_PURGE_PORT 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Force the Firmware to complete the current Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UMPC_COMPLETE_READ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Force UMP back into BOOT Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UMPC_HARDWARE_RESET 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Copy current download image to type 0xf2 record in 16k I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * firmware will change 0xff record to type 2 record when complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define UMPC_COPY_DNLD_TO_I2C 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Special function register commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * wIndex is register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * wValue is MSB/LSB mask/data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define UMPC_WRITE_SFR 0x83 /* Write SFR Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* wIndex is register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define UMPC_READ_SFR 0x84 /* Read SRF Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define UMPC_SET_CLR_DTR 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define UMPC_SET_CLR_RTS 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define UMPC_SET_CLR_LOOPBACK 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define UMPC_SET_CLR_BREAK 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Read MSR wIndex ModuleID (port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define UMPC_READ_MSR 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Toolkit commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Read-write group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define UMPC_MEMORY_READ 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define UMPC_MEMORY_WRITE 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * UMP DMA Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define UMPD_OEDB1_ADDRESS 0xFF08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define UMPD_OEDB2_ADDRESS 0xFF10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct out_endpoint_desc_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __u8 Configuration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __u8 XBufAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __u8 XByteCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __u8 Unused1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __u8 Unused2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __u8 YBufAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __u8 YByteCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __u8 BufferSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * TYPE DEFINITIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Structures for Firmware commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* UART settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct ump_uart_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __u16 wBaudRate; /* Baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __u16 wFlags; /* Bitmap mask of flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __u8 bDataBits; /* 5..8 - data bits per character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __u8 bParity; /* Parity settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __u8 bStopBits; /* Stop bits settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) char cXon; /* XON character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) char cXoff; /* XOFF character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __u8 bUartMode; /* Will be updated when a user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* interface is defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * TYPE DEFINITIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Structures for USB interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Interrupt packet structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct ump_interrupt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __u8 bICode; /* Interrupt code (interrupt num) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __u8 bIInfo; /* Interrupt information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TIUMP_GET_PORT_FROM_CODE(c) (((c) >> 6) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TIUMP_GET_FUNC_FROM_CODE(c) ((c) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TIUMP_INTERRUPT_CODE_LSR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TIUMP_INTERRUPT_CODE_MSR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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