^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * IONSP.H Definitions for I/O Networks Serial Protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1997-1998 Inside Out Networks, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * These definitions are used by both kernel-mode driver and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * peripheral firmware and MUST be kept in sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The data to and from all ports on the peripheral is multiplexed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) through a single endpoint pair (EP1 since it supports 64-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MaxPacketSize). Therefore, the data, commands, and status for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) each port must be preceded by a short header identifying the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) destination port. The header also identifies the bytes that follow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) as data or as command/status info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Header format, first byte:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) CLLLLPPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) | | |------ Port Number: 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) | |--------- Length: MSB bits of length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) |----------- Data/Command: 0 = Data header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 1 = Cmd / Status (Cmd if OUT, Status if IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) This gives 2 possible formats:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Data header: 0LLLLPPP LLLLLLLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Where (LLLL,LLLLLLL) is 12-bit length of data that follows for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) port number (PPP). The length is 0-based (0-FFF means 0-4095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bytes). The ~4K limit allows the host driver (which deals in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) transfer requests instead of individual packets) to write a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) large chunk of data in a single request. Note, however, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) the length must always be <= the current TxCredits for a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) port due to buffering limitations on the peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Cmd/Status header: 1ccccPPP [ CCCCCCCC, Params ]...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Where (cccc) or (cccc,CCCCCCCC) is the cmd or status identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Frequently-used values are encoded as (cccc), longer ones using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (cccc,CCCCCCCC). Subsequent bytes are optional parameters and are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) specific to the cmd or status code. This may include a length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) for command and status codes that need variable-length parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) In addition, we use another interrupt pipe (endpoint) which the host polls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) periodically for flow control information. The peripheral, when there has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) been a change, sends the following 10-byte packet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RRRRRRRRRRRRRRRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) T0T0T0T0T0T0T0T0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) T1T1T1T1T1T1T1T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) T2T2T2T2T2T2T2T2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) T3T3T3T3T3T3T3T3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) The first field is the 16-bit RxBytesAvail field, which indicates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) number of bytes which may be read by the host from EP1. This is necessary:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (a) because OSR2.1 has a bug which causes data loss if the peripheral returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) fewer bytes than the host expects to read, and (b) because, on Microsoft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) platforms at least, an outstanding read posted on EP1 consumes about 35% of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) the CPU just polling the device for data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) The next 4 fields are the 16-bit TxCredits for each port, which indicate how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) many bytes the host is allowed to send on EP1 for transmit to a given port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) After an OPEN_PORT command, the Edgeport sends the initial TxCredits for that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) All 16-bit fields are sent in little-endian (Intel) format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) // Define format of InterruptStatus packet returned from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) // Interrupt pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct int_status_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __u16 RxBytesAvail; // Additional bytes available to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) // be read from Bulk IN pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __u16 TxCredits[MAX_RS232_PORTS]; // Additional space available in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) // given port's TxBuffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GET_INT_STATUS_SIZE(NumPorts) (sizeof(__u16) + (sizeof(__u16) * (NumPorts)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) // Define cmd/status header values and macros to extract them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) // Data: 0LLLLPPP LLLLLLLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) // Cmd/Stat: 1ccccPPP CCCCCCCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IOSP_DATA_HDR_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IOSP_CMD_HDR_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IOSP_MAX_DATA_LENGTH 0x0FFF // 12 bits -> 4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IOSP_PORT_MASK 0x07 // Mask to isolate port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IOSP_CMD_STAT_BIT 0x80 // If set, this is command/status header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IS_CMD_STAT_HDR(Byte1) ((Byte1) & IOSP_CMD_STAT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IS_DATA_HDR(Byte1) (!IS_CMD_STAT_HDR(Byte1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IOSP_GET_HDR_PORT(Byte1) ((__u8) ((Byte1) & IOSP_PORT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IOSP_GET_HDR_DATA_LEN(Byte1, Byte2) ((__u16) (((__u16)((Byte1) & 0x78)) << 5) | (Byte2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IOSP_GET_STATUS_CODE(Byte1) ((__u8) (((Byte1) & 0x78) >> 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) // These macros build the 1st and 2nd bytes for a data header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IOSP_BUILD_DATA_HDR2(Port, Len) ((__u8) (Len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) // These macros build the 1st and 2nd bytes for a command header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) //--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) // Define values for commands and command parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) // (sent from Host to Edgeport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) // 1ccccPPP P1P1P1P1 [ P2P2P2P2P2 ]...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) // cccc: 00-07 2-byte commands. Write UART register 0-7 with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) // value in P1. See 16650.H for definitions of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) // UART register numbers and contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) // 08-0B 3-byte commands: ==== P1 ==== ==== P2 ====
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) // 08 available for expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) // 09 1-param commands Command Code Param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) // 0A available for expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) // 0B available for expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) // 0C-0D 4-byte commands. P1 = extended cmd and P2,P3 = params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) // Currently unimplemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) // 0E-0F N-byte commands: P1 = num bytes after P1 (ie, TotalLen - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) // P2 = extended cmd, P3..Pn = parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) // Currently unimplemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IOSP_WRITE_UART_REG(n) ((n) & 0x07) // UartReg[ n ] := P1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) // Register numbers and contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) // defined in 16554.H.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) // 0x08 // Available for expansion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IOSP_EXT_CMD 0x09 // P1 = Command code (defined below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) // P2 = Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) // Extended Command values, used with IOSP_EXT_CMD, may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) // or may not use parameter P2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IOSP_CMD_OPEN_PORT 0x00 // Enable ints, init UART. (NO PARAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IOSP_CMD_CLOSE_PORT 0x01 // Disable ints, flush buffers. (NO PARAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IOSP_CMD_CHASE_PORT 0x02 // Wait for Edgeport TX buffers to empty. (NO PARAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IOSP_CMD_SET_RX_FLOW 0x03 // Set Rx Flow Control in Edgeport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IOSP_CMD_SET_TX_FLOW 0x04 // Set Tx Flow Control in Edgeport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IOSP_CMD_SET_XON_CHAR 0x05 // Set XON Character in Edgeport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IOSP_CMD_SET_XOFF_CHAR 0x06 // Set XOFF Character in Edgeport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IOSP_CMD_RX_CHECK_REQ 0x07 // Request Edgeport to insert a Checkpoint into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) // the receive data stream (Parameter = 1 byte sequence number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IOSP_CMD_SET_BREAK 0x08 // Turn on the BREAK (LCR bit 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IOSP_CMD_CLEAR_BREAK 0x09 // Turn off the BREAK (LCR bit 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) // Define macros to simplify building of IOSP cmds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IOSP_WRITE_UART_REG(Reg)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (*(ppBuf))[1] = (Val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *ppBuf += 2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *pLen += 2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) (*(ppBuf))[1] = (ExtCmd); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) (*(ppBuf))[2] = (Param); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *ppBuf += 3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *pLen += 3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) //--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) // Define format of flow control commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) // (sent from Host to Edgeport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) // 11001PPP FlowCmd FlowTypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) // Note that the 'FlowTypes' parameter is a bit mask; that is,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) // more than one flow control type can be active at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) // FlowTypes = 0 means 'no flow control'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) // IOSP_CMD_SET_RX_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) // Tells Edgeport how it can stop incoming UART data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) // Example for Port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) // P0 = 11001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) // P1 = IOSP_CMD_SET_RX_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) // P2 = Bit mask as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IOSP_RX_FLOW_RTS 0x01 // Edgeport drops RTS to stop incoming data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IOSP_RX_FLOW_DTR 0x02 // Edgeport drops DTR to stop incoming data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IOSP_RX_FLOW_DSR_SENSITIVITY 0x04 // Ignores Rx data unless DSR high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) // Not currently implemented by firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IOSP_RX_FLOW_XON_XOFF 0x08 // Edgeport sends XOFF char to stop incoming data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) // Host must have previously programmed the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) // XON/XOFF values with SET_XON/SET_XOFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) // before enabling this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) // IOSP_CMD_SET_TX_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) // Tells Edgeport what signal(s) will stop it from transmitting UART data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) // Example for Port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) // P0 = 11001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) // P1 = IOSP_CMD_SET_TX_FLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) // P2 = Bit mask as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IOSP_TX_FLOW_CTS 0x01 // Edgeport stops Tx if CTS low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IOSP_TX_FLOW_DSR 0x02 // Edgeport stops Tx if DSR low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IOSP_TX_FLOW_DCD 0x04 // Edgeport stops Tx if DCD low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IOSP_TX_FLOW_XON_XOFF 0x08 // Edgeport stops Tx upon receiving XOFF char.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) // Host must have previously programmed the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) // XON/XOFF values with SET_XON/SET_XOFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) // before enabling this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IOSP_TX_FLOW_XOFF_CONTINUE 0x10 // If not set, Edgeport stops Tx when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) // sending XOFF in order to fix broken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) // systems that interpret the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) // received char as XON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) // If set, Edgeport continues Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) // normally after transmitting XOFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) // Not currently implemented by firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IOSP_TX_TOGGLE_RTS 0x20 // Edgeport drives RTS as a true half-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) // Request-to-Send signal: it is raised before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) // beginning transmission and lowered after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) // the last Tx char leaves the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) // Not currently implemented by firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) // IOSP_CMD_SET_XON_CHAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) // Sets the character which Edgeport transmits/interprets as XON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) // Note: This command MUST be sent before sending a SET_RX_FLOW or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) // SET_TX_FLOW with the XON_XOFF bit set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) // Example for Port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) // P0 = 11001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) // P1 = IOSP_CMD_SET_XON_CHAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) // P2 = 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) // IOSP_CMD_SET_XOFF_CHAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) // Sets the character which Edgeport transmits/interprets as XOFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) // Note: This command must be sent before sending a SET_RX_FLOW or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) // SET_TX_FLOW with the XON_XOFF bit set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) // Example for Port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) // P0 = 11001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) // P1 = IOSP_CMD_SET_XOFF_CHAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) // P2 = 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) // IOSP_CMD_RX_CHECK_REQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) // This command is used to assist in the implementation of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) // IOCTL_SERIAL_PURGE Windows IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) // This IOSP command tries to place a marker at the end of the RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) // queue in the Edgeport. If the Edgeport RX queue is full then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) // the Check will be discarded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) // It is up to the device driver to timeout waiting for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) // RX_CHECK_RSP. If a RX_CHECK_RSP is received, the driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) // sure that all data has been received from the edgeport and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) // may now purge any internal RX buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) // Note tat the sequence numbers may be used to detect lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) // CHECK_REQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) // Example for Port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) // P0 = 11001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) // P1 = IOSP_CMD_RX_CHECK_REQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) // P2 = Sequence number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) // Response will be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) // P1 = IOSP_EXT_RX_CHECK_RSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) // P2 = Request Sequence number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) //--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) // Define values for status and status parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) // (received by Host from Edgeport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) // 1ssssPPP P1P1P1P1 [ P2P2P2P2P2 ]...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) // ssss: 00-07 2-byte status. ssss identifies which UART register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) // has changed value, and the new value is in P1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) // Note that the ssss values do not correspond to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) // 16554 register numbers given in 16554.H. Instead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) // see below for definitions of the ssss numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) // used in this status message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) // 08-0B 3-byte status: ==== P1 ==== ==== P2 ====
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) // 08 LSR_DATA: New LSR Errored byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) // 09 1-param responses Response Code Param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) // 0A OPEN_RSP: InitialMsr TxBufferSize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) // 0B available for expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) // 0C-0D 4-byte status. P1 = extended status code and P2,P3 = params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) // Not currently implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) // 0E-0F N-byte status: P1 = num bytes after P1 (ie, TotalLen - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) // P2 = extended status, P3..Pn = parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) // Not currently implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /****************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * SSSS values for 2-byte status messages (0-8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IOSP_STATUS_LSR 0x00 // P1 is new value of LSR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) // Bits defined in 16554.H. Edgeport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) // returns this in order to report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) // line status errors (overrun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) // parity, framing, break). This form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) // is used when a errored receive data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) // character was NOT present in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) // UART when the LSR error occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) // (ie, when LSR bit 0 = 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IOSP_STATUS_MSR 0x01 // P1 is new value of MSR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) // Bits defined in 16554.H. Edgeport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) // returns this in order to report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) // changes in modem status lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) // (CTS, DSR, RI, CD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) // 0x02 // Available for future expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) // 0x03 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) // 0x04 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) // 0x05 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) // 0x06 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) // 0x07 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /****************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * SSSS values for 3-byte status messages (8-A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IOSP_STATUS_LSR_DATA 0x08 // P1 is new value of LSR register (same as STATUS_LSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) // P2 is errored character read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) // RxFIFO after LSR reported an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define IOSP_EXT_STATUS 0x09 // P1 is status/response code, param in P2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) // Response Codes (P1 values) for 3-byte status messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IOSP_EXT_STATUS_CHASE_RSP 0 // Reply to CHASE_PORT cmd. P2 is outcome:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IOSP_EXT_STATUS_CHASE_PASS 0 // P2 = 0: All Tx data drained successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IOSP_EXT_STATUS_CHASE_FAIL 1 // P2 = 1: Timed out (stuck due to flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) // control from remote device).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IOSP_EXT_STATUS_RX_CHECK_RSP 1 // Reply to RX_CHECK cmd. P2 is sequence number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define IOSP_STATUS_OPEN_RSP 0x0A // Reply to OPEN_PORT cmd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) // P1 is Initial MSR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) // P2 is encoded TxBuffer Size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) // TxBufferSize = (P2 + 1) * 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) // 0x0B // Available for future expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define GET_TX_BUFFER_SIZE(P2) (((P2) + 1) * 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /****************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * SSSS values for 4-byte status messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define IOSP_EXT4_STATUS 0x0C // Extended status code in P1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) // Params in P2, P3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) // Currently unimplemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) // 0x0D // Currently unused, available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) // Macros to parse status messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define IOSP_GET_STATUS_LEN(code) ((code) < 8 ? 2 : ((code) < 0x0A ? 3 : 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define IOSP_STATUS_IS_2BYTE(code) ((code) < 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define IOSP_STATUS_IS_3BYTE(code) (((code) >= 0x08) && ((code) <= 0x0B))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define IOSP_STATUS_IS_4BYTE(code) (((code) >= 0x0C) && ((code) <= 0x0D))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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