^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * 16654.H Definitions for 16C654 UART used on EdgePorts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998 Inside Out Networks, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #if !defined(_16654_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _16654_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * D e f i n e s / T y p e d e f s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) // UART register numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) // above are used internally to indicate that we must enable access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) // to them via LCR bit 0x80 or LCR = 0xBF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) // The register number sent to the Edgeport is then (x & 0x7).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) // Driver must not access registers that affect operation of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define THR 0 // ! Transmit Holding Register (Write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RDR 0 // ! Receive Holding Register (Read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IER 1 // ! Interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FCR 2 // ! Fifo Control Register (Write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ISR 2 // Interrupt Status Register (Read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LCR 3 // Line Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCR 4 // Modem Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LSR 5 // Line Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MSR 6 // Modem Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPR 7 // ScratchPad Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DLM 9 // Bank2[ 1 ] Divisor Latch MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EFR 10 // Bank2[ 2 ] Extended Function Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) //efine unused 11 // Bank2[ 3 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XON1 12 // Bank2[ 4 ] Xon-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define XON2 13 // Bank2[ 5 ] Xon-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XOFF1 14 // Bank2[ 6 ] Xoff-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XOFF2 15 // Bank2[ 7 ] Xoff-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NUM_16654_REGS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IS_REG_2ND_BANK(x) ((x) >= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) // Bit definitions for each register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IER_RX 0x01 // Enable receive interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IER_TX 0x02 // Enable transmit interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IER_RXS 0x04 // Enable receive status interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IER_MDM 0x08 // Enable modem status interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IER_SLEEP 0x10 // Enable sleep mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IER_XOFF 0x20 // Enable s/w flow control (XOFF) interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IER_RTS 0x40 // Enable RTS interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IER_CTS 0x80 // Enable CTS interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IER_ENABLE_ALL 0xFF // Enable all ints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FCR_FIFO_EN 0x01 // Enable FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FCR_RXCLR 0x02 // Reset Rx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FCR_TXCLR 0x04 // Reset Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FCR_DMA_BLK 0x08 // Enable DMA block mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FCR_TX_LEVEL_32 0x20 // Tx FIFO Level = 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FCR_TX_LEVEL_56 0x30 // Tx FIFO Level = 56 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FCR_RX_LEVEL_MASK 0xC0 // Mask for Rx FIFO Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FCR_RX_LEVEL_8 0x00 // Rx FIFO Level = 8 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FCR_RX_LEVEL_16 0x40 // Rx FIFO Level = 16 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FCR_RX_LEVEL_56 0x80 // Rx FIFO Level = 56 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FCR_RX_LEVEL_60 0xC0 // Rx FIFO Level = 60 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ISR_INT_MDM_STATUS 0x00 // Modem status int pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ISR_INT_NONE 0x01 // No interrupt pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ISR_INT_TXRDY 0x02 // Tx ready int pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ISR_INT_RXRDY 0x04 // Rx ready int pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ISR_INT_LINE_STATUS 0x06 // Line status int pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ISR_INT_RX_TIMEOUT 0x0C // Rx timeout int pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ISR_INT_RX_XOFF 0x10 // Rx Xoff int pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ISR_INT_RTS_CTS 0x20 // RTS/CTS change int pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ISR_FIFO_ENABLED 0xC0 // Bits set if FIFOs enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ISR_INT_BITS_MASK 0x3E // Mask to isolate valid int causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LCR_BITS_5 0x00 // 5 bits/char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LCR_BITS_6 0x01 // 6 bits/char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LCR_BITS_7 0x02 // 7 bits/char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LCR_BITS_8 0x03 // 8 bits/char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LCR_BITS_MASK 0x03 // Mask for bits/char field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LCR_STOP_1 0x00 // 1 stop bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LCR_STOP_1_5 0x04 // 1.5 stop bits (if 5 bits/char)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LCR_STOP_2 0x04 // 2 stop bits (if 6-8 bits/char)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LCR_STOP_MASK 0x04 // Mask for stop bits field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LCR_PAR_NONE 0x00 // No parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LCR_PAR_ODD 0x08 // Odd parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LCR_PAR_EVEN 0x18 // Even parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LCR_PAR_MARK 0x28 // Force parity bit to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LCR_PAR_SPACE 0x38 // Force parity bit to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LCR_PAR_MASK 0x38 // Mask for parity field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LCR_SET_BREAK 0x40 // Set Break condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LCR_DL_ENABLE 0x80 // Enable access to divisor latch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LCR_ACCESS_EFR 0xBF // Load this value to access DLL,DLM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) // and also the '654-only registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) // EFR, XON1, XON2, XOFF1, XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MCR_DTR 0x01 // Assert DTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MCR_RTS 0x02 // Assert RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCR_OUT1 0x04 // Loopback only: Sets state of RI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCR_MASTER_IE 0x08 // Enable interrupt outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCR_LOOPBACK 0x10 // Set internal (digital) loopback mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCR_XON_ANY 0x20 // Enable any char to exit XOFF mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCR_IR_ENABLE 0x40 // Enable IrDA functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCR_BRG_DIV_4 0x80 // Divide baud rate clk by /4 instead of /1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LSR_RX_AVAIL 0x01 // Rx data available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LSR_OVER_ERR 0x02 // Rx overrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LSR_PAR_ERR 0x04 // Rx parity error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LSR_FRM_ERR 0x08 // Rx framing error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LSR_BREAK 0x10 // Rx break condition detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LSR_TX_EMPTY 0x20 // Tx Fifo empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LSR_TX_ALL_EMPTY 0x40 // Tx Fifo and shift register empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LSR_FIFO_ERR 0x80 // Rx Fifo contains at least 1 erred char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EDGEPORT_MSR_DELTA_CTS 0x01 // CTS changed from last read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EDGEPORT_MSR_DELTA_DSR 0x02 // DSR changed from last read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EDGEPORT_MSR_DELTA_RI 0x04 // RI changed from 0 -> 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EDGEPORT_MSR_DELTA_CD 0x08 // CD changed from last read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EDGEPORT_MSR_CTS 0x10 // Current state of CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EDGEPORT_MSR_DSR 0x20 // Current state of DSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EDGEPORT_MSR_RI 0x40 // Current state of RI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EDGEPORT_MSR_CD 0x80 // Current state of CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) // Tx Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) //-------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EFR_SWFC_NONE 0x00 // None None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EFR_SWFC_RX1 0x02 // None XOFF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EFR_SWFC_RX2 0x01 // None XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EFR_SWFC_RX12 0x03 // None XOFF1 & XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EFR_SWFC_TX1 0x08 // XOFF1 None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EFR_SWFC_TX1_RX1 0x0a // XOFF1 XOFF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EFR_SWFC_TX1_RX2 0x09 // XOFF1 XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EFR_SWFC_TX1_RX12 0x0b // XOFF1 XOFF1 & XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EFR_SWFC_TX2 0x04 // XOFF2 None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EFR_SWFC_TX2_RX1 0x06 // XOFF2 XOFF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EFR_SWFC_TX2_RX2 0x05 // XOFF2 XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define EFR_SWFC_TX2_RX12 0x07 // XOFF2 XOFF1 & XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EFR_SWFC_TX12 0x0c // XOFF1 & XOFF2 None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EFR_SWFC_TX12_RX1 0x0e // XOFF1 & XOFF2 XOFF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EFR_SWFC_TX12_RX2 0x0d // XOFF1 & XOFF2 XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define EFR_SWFC_TX12_RX12 0x0f // XOFF1 & XOFF2 XOFF1 & XOFF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define EFR_TX_FC_MASK 0x0c // Mask to isolate Rx flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EFR_TX_FC_NONE 0x00 // No Tx Xon/Xoff flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define EFR_TX_FC_X1 0x08 // Transmit Xon1/Xoff1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EFR_TX_FC_X2 0x04 // Transmit Xon2/Xoff2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EFR_TX_FC_X1_2 0x0c // Transmit Xon1&2/Xoff1&2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EFR_RX_FC_MASK 0x03 // Mask to isolate Rx flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EFR_RX_FC_NONE 0x00 // No Rx Xon/Xoff flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EFR_RX_FC_X1 0x02 // Receiver compares Xon1/Xoff1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EFR_RX_FC_X2 0x01 // Receiver compares Xon2/Xoff2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EFR_RX_FC_X1_2 0x03 // Receiver compares Xon1&2/Xoff1&2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EFR_SWFC_MASK 0x0F // Mask for software flow control field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EFR_ENABLE_16654 0x10 // Enable 16C654 features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define EFR_SPEC_DETECT 0x20 // Enable special character detect interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EFR_AUTO_RTS 0x40 // Use RTS for Rx flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EFR_AUTO_CTS 0x80 // Use CTS for Tx flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif // if !defined(_16654_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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