^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * F81532/F81534 USB to Serial Ports Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * F81532 => 2 Serial Ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * F81534 => 4 Serial Ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2016 Feature Integration Technology Inc., (Fintek)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2016 Tom Tsai (Tom_Tsai@fintek.com.tw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2016 Peter Hong (Peter_Hong@fintek.com.tw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The F81532/F81534 had 1 control endpoint for setting, 1 endpoint bulk-out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * for all serial port TX and 1 endpoint bulk-in for all serial port read in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * (Read Data/MSR/LSR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Write URB is fixed with 512bytes, per serial port used 128Bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * It can be described by f81534_prepare_write_buffer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Read URB is 512Bytes max, per serial port used 128Bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * It can be described by f81534_process_read_urb() and maybe received with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 128x1,2,3,4 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/usb/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Serial Port register Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define F81534_UART_BASE_ADDRESS 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define F81534_UART_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define F81534_DIVISOR_LSB_REG (0x00 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define F81534_DIVISOR_MSB_REG (0x01 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define F81534_INTERRUPT_ENABLE_REG (0x01 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define F81534_FIFO_CONTROL_REG (0x02 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define F81534_LINE_CONTROL_REG (0x03 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define F81534_MODEM_CONTROL_REG (0x04 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define F81534_LINE_STATUS_REG (0x05 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define F81534_MODEM_STATUS_REG (0x06 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define F81534_CLOCK_REG (0x08 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define F81534_CONFIG1_REG (0x09 + F81534_UART_BASE_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define F81534_DEF_CONF_ADDRESS_START 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define F81534_DEF_CONF_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define F81534_CUSTOM_ADDRESS_START 0x2f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define F81534_CUSTOM_DATA_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define F81534_CUSTOM_NO_CUSTOM_DATA 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define F81534_CUSTOM_VALID_TOKEN 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define F81534_CONF_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define F81534_CONF_INIT_GPIO_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define F81534_CONF_WORK_GPIO_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define F81534_CONF_GPIO_SHUTDOWN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define F81534_CONF_GPIO_RS232 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define F81534_MAX_DATA_BLOCK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define F81534_MAX_BUS_RETRY 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Default URB timeout for USB operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define F81534_USB_MAX_RETRY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define F81534_USB_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define F81534_SET_GET_REGISTER 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define F81534_NUM_PORT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define F81534_UNUSED_PORT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define F81534_WRITE_BUFFER_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRIVER_DESC "Fintek F81532/F81534"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FINTEK_VENDOR_ID_1 0x1934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FINTEK_VENDOR_ID_2 0x2C42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FINTEK_DEVICE_ID 0x1202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define F81534_MAX_TX_SIZE 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define F81534_MAX_RX_SIZE 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define F81534_RECEIVE_BLOCK_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define F81534_MAX_RECEIVE_BLOCK_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define F81534_TOKEN_RECEIVE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define F81534_TOKEN_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define F81534_TOKEN_TX_EMPTY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define F81534_TOKEN_MSR_CHANGE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * We used interal SPI bus to access FLASH section. We must wait the SPI bus to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * idle if we performed any command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * SPI Bus status register: F81534_BUS_REG_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Bit 0/1 : BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Bit 2 : IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define F81534_BUS_BUSY (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define F81534_BUS_IDLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define F81534_BUS_READ_DATA 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define F81534_BUS_REG_STATUS 0x1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define F81534_BUS_REG_START 0x1002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define F81534_BUS_REG_END 0x1001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define F81534_CMD_READ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define F81534_DEFAULT_BAUD_RATE 9600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define F81534_PORT_CONF_RS232 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define F81534_PORT_CONF_RS485 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define F81534_PORT_CONF_RS485_INVERT (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define F81534_PORT_CONF_MODE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define F81534_PORT_CONF_DISABLE_PORT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define F81534_PORT_CONF_NOT_EXIST_PORT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define F81534_PORT_UNAVAILABLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (F81534_PORT_CONF_DISABLE_PORT | F81534_PORT_CONF_NOT_EXIST_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define F81534_1X_RXTRIGGER 0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define F81534_8X_RXTRIGGER 0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * F81532/534 Clock registers (offset +08h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Bit0: UART Enable (always on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Bit2-1: Clock source selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * 00: 1.846MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * 01: 18.46MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * 10: 24MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * 11: 14.77MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Bit4: Auto direction(RTS) control (RTS pin Low when TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Bit5: Invert direction(RTS) when Bit4 enabled (RTS pin high when TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define F81534_UART_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define F81534_CLK_1_846_MHZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define F81534_CLK_18_46_MHZ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define F81534_CLK_24_MHZ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define F81534_CLK_14_77_MHZ (BIT(1) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define F81534_CLK_MASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define F81534_CLK_TX_DELAY_1BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define F81534_CLK_RS485_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define F81534_CLK_RS485_INVERT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct usb_device_id f81534_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { USB_DEVICE(FINTEK_VENDOR_ID_1, FINTEK_DEVICE_ID) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { USB_DEVICE(FINTEK_VENDOR_ID_2, FINTEK_DEVICE_ID) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {} /* Terminating entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define F81534_TX_EMPTY_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct f81534_serial_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 conf_data[F81534_DEF_CONF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int tty_idx[F81534_NUM_PORT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 setting_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int opened_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct mutex urb_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct f81534_port_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct mutex mcr_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct mutex lcr_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct work_struct lsr_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct usb_serial_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long tx_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spinlock_t msr_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 baud_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 shadow_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 shadow_lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 shadow_msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 shadow_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 phy_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct f81534_pin_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const u16 reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const u8 reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct f81534_port_out_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct f81534_pin_data pin[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Pin output value for M2/M1/M0(SD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct f81534_port_out_pin f81534_port_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { { { 0x2ae8, BIT(7) }, { 0x2a90, BIT(5) }, { 0x2a90, BIT(4) } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { { { 0x2ae8, BIT(6) }, { 0x2ae8, BIT(0) }, { 0x2ae8, BIT(3) } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { { { 0x2a90, BIT(0) }, { 0x2ae8, BIT(2) }, { 0x2a80, BIT(6) } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { { { 0x2a90, BIT(3) }, { 0x2a90, BIT(2) }, { 0x2a90, BIT(1) } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static u32 const baudrate_table[] = { 115200, 921600, 1152000, 1500000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static u8 const clock_table[] = { F81534_CLK_1_846_MHZ, F81534_CLK_14_77_MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) F81534_CLK_18_46_MHZ, F81534_CLK_24_MHZ };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int f81534_logic_to_phy_port(struct usb_serial *serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct usb_serial_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct f81534_serial_private *serial_priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) usb_get_serial_data(port->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (i = 0; i < F81534_NUM_PORT; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (serial_priv->conf_data[i] & F81534_PORT_UNAVAILABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (port->port_number == count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ++count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int f81534_set_register(struct usb_serial *serial, u16 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct usb_interface *interface = serial->interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct usb_device *dev = serial->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) size_t count = F81534_USB_MAX_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tmp = kmalloc(sizeof(u8), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *tmp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Our device maybe not reply when heavily loading, We'll retry for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * F81534_USB_MAX_RETRY times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) status = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) F81534_SET_GET_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) USB_TYPE_VENDOR | USB_DIR_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) reg, 0, tmp, sizeof(u8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) F81534_USB_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (status > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } else if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(&interface->dev, "%s: reg: %x data: %x failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __func__, reg, data, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int f81534_get_register(struct usb_serial *serial, u16 reg, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct usb_interface *interface = serial->interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct usb_device *dev = serial->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) size_t count = F81534_USB_MAX_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tmp = kmalloc(sizeof(u8), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Our device maybe not reply when heavily loading, We'll retry for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * F81534_USB_MAX_RETRY times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) status = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) F81534_SET_GET_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) USB_TYPE_VENDOR | USB_DIR_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) reg, 0, tmp, sizeof(u8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) F81534_USB_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (status > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } else if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(&interface->dev, "%s: reg: %x failed: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) reg, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *data = *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int f81534_set_mask_register(struct usb_serial *serial, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 mask, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) status = f81534_get_register(serial, reg, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tmp |= (mask & data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return f81534_set_register(serial, reg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int f81534_set_phy_port_register(struct usb_serial *serial, int phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u16 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return f81534_set_register(serial, reg + F81534_UART_OFFSET * phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int f81534_get_phy_port_register(struct usb_serial *serial, int phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u16 reg, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return f81534_get_register(serial, reg + F81534_UART_OFFSET * phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int f81534_set_port_register(struct usb_serial_port *port, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return f81534_set_register(port->serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) reg + port_priv->phy_num * F81534_UART_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int f81534_get_port_register(struct usb_serial_port *port, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return f81534_get_register(port->serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) reg + port_priv->phy_num * F81534_UART_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * If we try to access the internal flash via SPI bus, we should check the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * status for every command. e.g., F81534_BUS_REG_START/F81534_BUS_REG_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int f81534_wait_for_spi_idle(struct usb_serial *serial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) size_t count = F81534_MAX_BUS_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) status = f81534_get_register(serial, F81534_BUS_REG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (tmp & F81534_BUS_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (tmp & F81534_BUS_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } while (--count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(&serial->interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "%s: timed out waiting for idle SPI bus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return f81534_set_register(serial, F81534_BUS_REG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tmp & ~F81534_BUS_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int f81534_get_spi_register(struct usb_serial *serial, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) status = f81534_get_register(serial, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return f81534_wait_for_spi_idle(serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int f81534_set_spi_register(struct usb_serial *serial, u16 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) status = f81534_set_register(serial, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return f81534_wait_for_spi_idle(serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int f81534_read_flash(struct usb_serial *serial, u32 address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) size_t size, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u8 tmp_buf[F81534_MAX_DATA_BLOCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) size_t block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) size_t read_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) size_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u16 reg_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) status = f81534_set_spi_register(serial, F81534_BUS_REG_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) F81534_CMD_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) status = f81534_set_spi_register(serial, F81534_BUS_REG_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) (address >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) status = f81534_set_spi_register(serial, F81534_BUS_REG_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (address >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) status = f81534_set_spi_register(serial, F81534_BUS_REG_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) (address >> 0) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Continuous read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) read_size = min_t(size_t, F81534_MAX_DATA_BLOCK, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) for (count = 0; count < read_size; ++count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* To write F81534_BUS_REG_END when final byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (size <= F81534_MAX_DATA_BLOCK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) read_size == count + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) reg_tmp = F81534_BUS_REG_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) reg_tmp = F81534_BUS_REG_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Dummy code, force IC to generate a read pulse, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * set of value 0xf1 is dont care (any value is ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) status = f81534_set_spi_register(serial, reg_tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0xf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) status = f81534_get_spi_register(serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) F81534_BUS_READ_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &tmp_buf[count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) offset = count + block * F81534_MAX_DATA_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) buf[offset] = tmp_buf[count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) size -= read_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ++block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } while (size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static void f81534_prepare_write_buffer(struct usb_serial_port *port, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int phy_num = port_priv->phy_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * The block layout is fixed with 4x128 Bytes, per 128 Bytes a port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * index 0: port phy idx (e.g., 0,1,2,3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * index 1: only F81534_TOKEN_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * index 2: serial TX out length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * index 3: fix to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * index 4~127: serial out data block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) for (i = 0; i < F81534_NUM_PORT; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) buf[i * F81534_RECEIVE_BLOCK_SIZE] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) buf[i * F81534_RECEIVE_BLOCK_SIZE + 1] = F81534_TOKEN_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) buf[i * F81534_RECEIVE_BLOCK_SIZE + 2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) buf[i * F81534_RECEIVE_BLOCK_SIZE + 3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tx_len = kfifo_out_locked(&port->write_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) &buf[phy_num * F81534_RECEIVE_BLOCK_SIZE + 4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) F81534_MAX_TX_SIZE, &port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) buf[phy_num * F81534_RECEIVE_BLOCK_SIZE + 2] = tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int f81534_submit_writer(struct usb_serial_port *port, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Check is any data in write_fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (kfifo_is_empty(&port->write_fifo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Check H/W is TXEMPTY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!test_and_clear_bit(F81534_TX_EMPTY_BIT, &port_priv->tx_empty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) urb = port->write_urbs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) f81534_prepare_write_buffer(port, port->bulk_out_buffers[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) urb->transfer_buffer_length = F81534_WRITE_BUFFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) result = usb_submit_urb(urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) set_bit(F81534_TX_EMPTY_BIT, &port_priv->tx_empty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(&port->dev, "%s: submit failed: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) usb_serial_port_softint(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static u32 f81534_calc_baud_divisor(u32 baudrate, u32 clockrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!baudrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Round to nearest divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return DIV_ROUND_CLOSEST(clockrate, baudrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int f81534_find_clk(u32 baudrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) for (idx = 0; idx < ARRAY_SIZE(baudrate_table); ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (baudrate <= baudrate_table[idx] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) baudrate_table[idx] % baudrate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int f81534_set_port_config(struct usb_serial_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct tty_struct *tty, u32 baudrate, u32 old_baudrate, u8 lcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 baud_list[] = {baudrate, old_baudrate, F81534_DEFAULT_BAUD_RATE};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (i = 0; i < ARRAY_SIZE(baud_list); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) idx = f81534_find_clk(baud_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (idx >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) baudrate = baud_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) tty_encode_baud_rate(tty, baudrate, baudrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) port_priv->baud_base = baudrate_table[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) port_priv->shadow_clk &= ~F81534_CLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) port_priv->shadow_clk |= clock_table[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) status = f81534_set_port_register(port, F81534_CLOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) port_priv->shadow_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_err(&port->dev, "CLOCK_REG setting failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (baudrate <= 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) value = F81534_1X_RXTRIGGER; /* 128 FIFO & TL: 1x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) value = F81534_8X_RXTRIGGER; /* 128 FIFO & TL: 8x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) status = f81534_set_port_register(port, F81534_CONFIG1_REG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_err(&port->dev, "%s: CONFIG1 setting failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (baudrate <= 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) value = UART_FCR_TRIGGER_1 | UART_FCR_ENABLE_FIFO; /* TL: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) value = UART_FCR_TRIGGER_8 | UART_FCR_ENABLE_FIFO; /* TL: 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) status = f81534_set_port_register(port, F81534_FIFO_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_err(&port->dev, "%s: FCR setting failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) divisor = f81534_calc_baud_divisor(baudrate, port_priv->baud_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mutex_lock(&port_priv->lcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) value = UART_LCR_DLAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) status = f81534_set_port_register(port, F81534_LINE_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(&port->dev, "%s: set LCR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) value = divisor & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) status = f81534_set_port_register(port, F81534_DIVISOR_LSB_REG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_err(&port->dev, "%s: set DLAB LSB failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) value = (divisor >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) status = f81534_set_port_register(port, F81534_DIVISOR_MSB_REG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dev_err(&port->dev, "%s: set DLAB MSB failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) value = lcr | (port_priv->shadow_lcr & UART_LCR_SBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) status = f81534_set_port_register(port, F81534_LINE_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_err(&port->dev, "%s: set LCR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) port_priv->shadow_lcr = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mutex_unlock(&port_priv->lcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void f81534_break_ctl(struct tty_struct *tty, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct usb_serial_port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mutex_lock(&port_priv->lcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) port_priv->shadow_lcr |= UART_LCR_SBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) port_priv->shadow_lcr &= ~UART_LCR_SBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) status = f81534_set_port_register(port, F81534_LINE_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) port_priv->shadow_lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(&port->dev, "set break failed: %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mutex_unlock(&port_priv->lcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int f81534_update_mctrl(struct usb_serial_port *port, unsigned int set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (((set | clear) & (TIOCM_DTR | TIOCM_RTS)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0; /* no change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mutex_lock(&port_priv->mcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* 'Set' takes precedence over 'Clear' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) clear &= ~set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Always enable UART_MCR_OUT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) tmp = UART_MCR_OUT2 | port_priv->shadow_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (clear & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) tmp &= ~UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (clear & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) tmp &= ~UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (set & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) tmp |= UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (set & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tmp |= UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) status = f81534_set_port_register(port, F81534_MODEM_CONTROL_REG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_err(&port->dev, "%s: MCR write failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mutex_unlock(&port_priv->mcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) port_priv->shadow_mcr = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mutex_unlock(&port_priv->mcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * This function will search the data area with token F81534_CUSTOM_VALID_TOKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * for latest configuration index. If nothing found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * (*index = F81534_CUSTOM_NO_CUSTOM_DATA), We'll load default configure in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * F81534_DEF_CONF_ADDRESS_START section.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * Due to we only use block0 to save data, so *index should be 0 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * F81534_CUSTOM_NO_CUSTOM_DATA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int f81534_find_config_idx(struct usb_serial *serial, u8 *index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) status = f81534_read_flash(serial, F81534_CUSTOM_ADDRESS_START, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_err(&serial->interface->dev, "%s: read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* We'll use the custom data when the data is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (tmp == F81534_CUSTOM_VALID_TOKEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) *index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *index = F81534_CUSTOM_NO_CUSTOM_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * The F81532/534 will not report serial port to USB serial subsystem when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * H/W DCD/DSR/CTS/RI/RX pin connected to ground.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * To detect RX pin status, we'll enable MCR interal loopback, disable it and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * delayed for 60ms. It connected to ground If LSR register report UART_LSR_BI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static bool f81534_check_port_hw_disabled(struct usb_serial *serial, int phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u8 old_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u8 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u8 lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u8 msr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) msr_mask = UART_MSR_DCD | UART_MSR_RI | UART_MSR_DSR | UART_MSR_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) status = f81534_get_phy_port_register(serial, phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) F81534_MODEM_STATUS_REG, &msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if ((msr & msr_mask) != msr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) status = f81534_set_phy_port_register(serial, phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) F81534_FIFO_CONTROL_REG, UART_FCR_ENABLE_FIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) status = f81534_get_phy_port_register(serial, phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) F81534_MODEM_CONTROL_REG, &old_mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) status = f81534_set_phy_port_register(serial, phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) F81534_MODEM_CONTROL_REG, UART_MCR_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) status = f81534_set_phy_port_register(serial, phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) F81534_MODEM_CONTROL_REG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) status = f81534_get_phy_port_register(serial, phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) F81534_LINE_STATUS_REG, &lsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) status = f81534_set_phy_port_register(serial, phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) F81534_MODEM_CONTROL_REG, old_mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if ((lsr & UART_LSR_BI) == UART_LSR_BI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * We had 2 generation of F81532/534 IC. All has an internal storage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * 1st is pure USB-to-TTL RS232 IC and designed for 4 ports only, no any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * internal data will used. All mode and gpio control should manually set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * by AP or Driver and all storage space value are 0xff. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * f81534_calc_num_ports() will run to final we marked as "oldest version"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * for this IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * 2rd is designed to more generic to use any transceiver and this is our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * mass production type. We'll save data in F81534_CUSTOM_ADDRESS_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * (0x2f00) with 9bytes. The 1st byte is a indicater. If the token is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * F81534_CUSTOM_VALID_TOKEN(0xf0), the IC is 2nd gen type, the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * 4bytes save port mode (0:RS232/1:RS485 Invert/2:RS485), and the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * 4bytes save GPIO state(value from 0~7 to represent 3 GPIO output pin).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * The f81534_calc_num_ports() will run to "new style" with checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * F81534_PORT_UNAVAILABLE section.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int f81534_calc_num_ports(struct usb_serial *serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct usb_serial_endpoints *epds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct f81534_serial_private *serial_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct device *dev = &serial->interface->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int size_bulk_in = usb_endpoint_maxp(epds->bulk_in[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int size_bulk_out = usb_endpoint_maxp(epds->bulk_out[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 num_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (size_bulk_out != F81534_WRITE_BUFFER_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) size_bulk_in != F81534_MAX_RECEIVE_BLOCK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(dev, "unsupported endpoint max packet size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) serial_priv = devm_kzalloc(&serial->interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) sizeof(*serial_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (!serial_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) usb_set_serial_data(serial, serial_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) mutex_init(&serial_priv->urb_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Check had custom setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) status = f81534_find_config_idx(serial, &serial_priv->setting_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dev_err(&serial->interface->dev, "%s: find idx failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * We'll read custom data only when data available, otherwise we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * read default value instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (serial_priv->setting_idx != F81534_CUSTOM_NO_CUSTOM_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) status = f81534_read_flash(serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) F81534_CUSTOM_ADDRESS_START +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) F81534_CONF_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) sizeof(serial_priv->conf_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) serial_priv->conf_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_err(&serial->interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "%s: get custom data failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_dbg(&serial->interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "%s: read config from block: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) serial_priv->setting_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* Read default board setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) status = f81534_read_flash(serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) F81534_DEF_CONF_ADDRESS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) sizeof(serial_priv->conf_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) serial_priv->conf_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev_err(&serial->interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "%s: read failed: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_dbg(&serial->interface->dev, "%s: read default config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* New style, find all possible ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) for (i = 0; i < F81534_NUM_PORT; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (f81534_check_port_hw_disabled(serial, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) serial_priv->conf_data[i] |= F81534_PORT_UNAVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (serial_priv->conf_data[i] & F81534_PORT_UNAVAILABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ++num_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!num_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev_warn(&serial->interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "no config found, assuming 4 ports\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) num_port = 4; /* Nothing found, oldest version IC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Assign phy-to-logic mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) for (i = 0; i < F81534_NUM_PORT; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (serial_priv->conf_data[i] & F81534_PORT_UNAVAILABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) serial_priv->tty_idx[i] = index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev_dbg(&serial->interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "%s: phy_num: %d, tty_idx: %d\n", __func__, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) serial_priv->tty_idx[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * Setup bulk-out endpoint multiplexing. All ports share the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * bulk-out endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) BUILD_BUG_ON(ARRAY_SIZE(epds->bulk_out) < F81534_NUM_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) for (i = 1; i < num_port; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) epds->bulk_out[i] = epds->bulk_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) epds->num_bulk_out = num_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return num_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static void f81534_set_termios(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct usb_serial_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct ktermios *old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) u8 new_lcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u32 baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 old_baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (C_BAUD(tty) == B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) f81534_update_mctrl(port, 0, TIOCM_DTR | TIOCM_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) else if (old_termios && (old_termios->c_cflag & CBAUD) == B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) f81534_update_mctrl(port, TIOCM_DTR | TIOCM_RTS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (C_PARENB(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) new_lcr |= UART_LCR_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!C_PARODD(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) new_lcr |= UART_LCR_EPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (C_CMSPAR(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) new_lcr |= UART_LCR_SPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (C_CSTOPB(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) new_lcr |= UART_LCR_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) switch (C_CSIZE(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) new_lcr |= UART_LCR_WLEN5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) new_lcr |= UART_LCR_WLEN6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) new_lcr |= UART_LCR_WLEN7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) new_lcr |= UART_LCR_WLEN8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) baud = tty_get_baud_rate(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) old_baud = tty_termios_baud_rate(old_termios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) old_baud = F81534_DEFAULT_BAUD_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_dbg(&port->dev, "%s: baud: %d\n", __func__, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) status = f81534_set_port_config(port, tty, baud, old_baud, new_lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev_err(&port->dev, "%s: set port config failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static int f81534_submit_read_urb(struct usb_serial *serial, gfp_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return usb_serial_generic_submit_read_urbs(serial->port[0], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static void f81534_msr_changed(struct usb_serial_port *port, u8 msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct tty_struct *tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u8 old_msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (!(msr & UART_MSR_ANY_DELTA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) spin_lock_irqsave(&port_priv->msr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) old_msr = port_priv->shadow_msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) port_priv->shadow_msr = msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) spin_unlock_irqrestore(&port_priv->msr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_dbg(&port->dev, "%s: MSR from %02x to %02x\n", __func__, old_msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Update input line counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (msr & UART_MSR_DCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) port->icount.cts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (msr & UART_MSR_DDSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) port->icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (msr & UART_MSR_DDCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) port->icount.dcd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (msr & UART_MSR_TERI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) port->icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) wake_up_interruptible(&port->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (!(msr & UART_MSR_DDCD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) dev_dbg(&port->dev, "%s: DCD Changed: phy_num: %d from %x to %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) __func__, port_priv->phy_num, old_msr, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) tty = tty_port_tty_get(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (!tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) usb_serial_handle_dcd_change(port, tty, msr & UART_MSR_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) tty_kref_put(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int f81534_read_msr(struct usb_serial_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u8 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Get MSR initial value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) status = f81534_get_port_register(port, F81534_MODEM_STATUS_REG, &msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Force update current state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) spin_lock_irqsave(&port_priv->msr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) port_priv->shadow_msr = msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) spin_unlock_irqrestore(&port_priv->msr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static int f81534_open(struct tty_struct *tty, struct usb_serial_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct f81534_serial_private *serial_priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) usb_get_serial_data(port->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) status = f81534_set_port_register(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) F81534_FIFO_CONTROL_REG, UART_FCR_ENABLE_FIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) dev_err(&port->dev, "%s: Clear FIFO failed: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) f81534_set_termios(tty, port, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) status = f81534_read_msr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) mutex_lock(&serial_priv->urb_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Submit Read URBs for first port opened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!serial_priv->opened_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) status = f81534_submit_read_urb(port->serial, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) serial_priv->opened_port++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) mutex_unlock(&serial_priv->urb_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) set_bit(F81534_TX_EMPTY_BIT, &port_priv->tx_empty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static void f81534_close(struct usb_serial_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct f81534_serial_private *serial_priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) usb_get_serial_data(port->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct usb_serial_port *port0 = port->serial->port[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) usb_kill_urb(port->write_urbs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) kfifo_reset_out(&port->write_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Kill Read URBs when final port closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) mutex_lock(&serial_priv->urb_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) serial_priv->opened_port--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!serial_priv->opened_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) for (i = 0; i < ARRAY_SIZE(port0->read_urbs); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) usb_kill_urb(port0->read_urbs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) mutex_unlock(&serial_priv->urb_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int f81534_get_serial_info(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct serial_struct *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct usb_serial_port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct f81534_port_private *port_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ss->type = PORT_16550A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ss->port = port->port_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ss->line = port->minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ss->baud_base = port_priv->baud_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static void f81534_process_per_serial_block(struct usb_serial_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) int phy_num = data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) size_t read_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) char tty_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u8 lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * The block layout is 128 Bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * index 0: port phy idx (e.g., 0,1,2,3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * index 1: It's could be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * F81534_TOKEN_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * F81534_TOKEN_TX_EMPTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * F81534_TOKEN_MSR_CHANGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * index 2: serial in size (data+lsr, must be even)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * meaningful for F81534_TOKEN_RECEIVE only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * index 3: current MSR with this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * index 4~127: serial in data block (data+lsr, must be even)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) switch (data[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case F81534_TOKEN_TX_EMPTY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) set_bit(F81534_TX_EMPTY_BIT, &port_priv->tx_empty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Try to submit writer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) status = f81534_submit_writer(port, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dev_err(&port->dev, "%s: submit failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) case F81534_TOKEN_MSR_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) f81534_msr_changed(port, data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case F81534_TOKEN_RECEIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) read_size = data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (read_size > F81534_MAX_RX_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dev_err(&port->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "%s: phy: %d read_size: %zu larger than: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) __func__, phy_num, read_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) F81534_MAX_RX_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dev_warn(&port->dev, "%s: unknown token: %02x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) for (i = 4; i < 4 + read_size; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) tty_flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) lsr = data[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (lsr & UART_LSR_BRK_ERROR_BITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (lsr & UART_LSR_BI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) tty_flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) usb_serial_handle_break(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) } else if (lsr & UART_LSR_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) tty_flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) } else if (lsr & UART_LSR_FE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) tty_flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (lsr & UART_LSR_OE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) tty_insert_flip_char(&port->port, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) schedule_work(&port_priv->lsr_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (port->sysrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (usb_serial_handle_sysrq_char(port, data[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) tty_insert_flip_char(&port->port, data[i], tty_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) tty_flip_buffer_push(&port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static void f81534_process_read_urb(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct f81534_serial_private *serial_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct usb_serial_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct usb_serial *serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) int phy_port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) int tty_port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (!urb->actual_length ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) urb->actual_length % F81534_RECEIVE_BLOCK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) port = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) serial = port->serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) buf = urb->transfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) serial_priv = usb_get_serial_data(serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) for (i = 0; i < urb->actual_length; i += F81534_RECEIVE_BLOCK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) phy_port_num = buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (phy_port_num >= F81534_NUM_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev_err(&port->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) "%s: phy_port_num: %d larger than: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) __func__, phy_port_num, F81534_NUM_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) tty_port_num = serial_priv->tty_idx[phy_port_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) port = serial->port[tty_port_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (tty_port_initialized(&port->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) f81534_process_per_serial_block(port, &buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static void f81534_write_usb_callback(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct usb_serial_port *port = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) switch (urb->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) case -ENOENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case -ECONNRESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) case -ESHUTDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dev_dbg(&port->dev, "%s - urb stopped: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) __func__, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) case -EPIPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_err(&port->dev, "%s - urb stopped: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) __func__, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev_dbg(&port->dev, "%s - nonzero urb status: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) __func__, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static void f81534_lsr_worker(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct f81534_port_private *port_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct usb_serial_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) port_priv = container_of(work, struct f81534_port_private, lsr_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) port = port_priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) status = f81534_get_port_register(port, F81534_LINE_STATUS_REG, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_warn(&port->dev, "read LSR failed: %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static int f81534_set_port_output_pin(struct usb_serial_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) struct f81534_serial_private *serial_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) struct f81534_port_private *port_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct usb_serial *serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) const struct f81534_port_out_pin *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) u8 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) serial = port->serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) serial_priv = usb_get_serial_data(serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) idx = F81534_CONF_INIT_GPIO_OFFSET + port_priv->phy_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) value = serial_priv->conf_data[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (value >= F81534_CONF_GPIO_SHUTDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * Newer IC configure will make transceiver in shutdown mode on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * initial power on. We need enable it before using UARTs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) idx = F81534_CONF_WORK_GPIO_OFFSET + port_priv->phy_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) value = serial_priv->conf_data[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (value >= F81534_CONF_GPIO_SHUTDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) value = F81534_CONF_GPIO_RS232;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) pins = &f81534_port_out_pins[port_priv->phy_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) for (i = 0; i < ARRAY_SIZE(pins->pin); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) status = f81534_set_mask_register(serial,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pins->pin[i].reg_addr, pins->pin[i].reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) value & BIT(i) ? pins->pin[i].reg_mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dev_dbg(&port->dev, "Output pin (M0/M1/M2): %d\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static int f81534_port_probe(struct usb_serial_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct f81534_serial_private *serial_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct f81534_port_private *port_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) serial_priv = usb_get_serial_data(port->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) port_priv = devm_kzalloc(&port->dev, sizeof(*port_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (!port_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * We'll make tx frame error when baud rate from 384~500kps. So we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * delay all tx data frame with 1bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) port_priv->shadow_clk = F81534_UART_EN | F81534_CLK_TX_DELAY_1BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) spin_lock_init(&port_priv->msr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) mutex_init(&port_priv->mcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) mutex_init(&port_priv->lcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) INIT_WORK(&port_priv->lsr_work, f81534_lsr_worker);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* Assign logic-to-phy mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ret = f81534_logic_to_phy_port(port->serial, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) port_priv->phy_num = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) port_priv->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) usb_set_serial_port_data(port, port_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dev_dbg(&port->dev, "%s: port_number: %d, phy_num: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) port->port_number, port_priv->phy_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * The F81532/534 will hang-up when enable LSR interrupt in IER and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * occur data overrun. So we'll disable the LSR interrupt in probe()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * and submit the LSR worker to clear LSR state when reported LSR error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * bit with bulk-in data in f81534_process_per_serial_block().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret = f81534_set_port_register(port, F81534_INTERRUPT_ENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) UART_IER_RDI | UART_IER_THRI | UART_IER_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) value = serial_priv->conf_data[port_priv->phy_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) switch (value & F81534_PORT_CONF_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case F81534_PORT_CONF_RS485_INVERT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) port_priv->shadow_clk |= F81534_CLK_RS485_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) F81534_CLK_RS485_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_dbg(&port->dev, "RS485 invert mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) case F81534_PORT_CONF_RS485:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) port_priv->shadow_clk |= F81534_CLK_RS485_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_dbg(&port->dev, "RS485 mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) case F81534_PORT_CONF_RS232:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) dev_dbg(&port->dev, "RS232 mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return f81534_set_port_output_pin(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static int f81534_port_remove(struct usb_serial_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) flush_work(&port_priv->lsr_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static int f81534_tiocmget(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct usb_serial_port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) u8 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) u8 mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* Read current MSR from device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) status = f81534_get_port_register(port, F81534_MODEM_STATUS_REG, &msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) mutex_lock(&port_priv->mcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) mcr = port_priv->shadow_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) mutex_unlock(&port_priv->mcr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) r = (mcr & UART_MCR_DTR ? TIOCM_DTR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) (mcr & UART_MCR_RTS ? TIOCM_RTS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) (msr & UART_MSR_CTS ? TIOCM_CTS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) (msr & UART_MSR_DCD ? TIOCM_CAR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) (msr & UART_MSR_RI ? TIOCM_RI : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) (msr & UART_MSR_DSR ? TIOCM_DSR : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static int f81534_tiocmset(struct tty_struct *tty, unsigned int set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct usb_serial_port *port = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return f81534_update_mctrl(port, set, clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static void f81534_dtr_rts(struct usb_serial_port *port, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) f81534_update_mctrl(port, TIOCM_DTR | TIOCM_RTS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) f81534_update_mctrl(port, 0, TIOCM_DTR | TIOCM_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int f81534_write(struct tty_struct *tty, struct usb_serial_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) const u8 *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) int bytes_out, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) bytes_out = kfifo_in_locked(&port->write_fifo, buf, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) &port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) status = f81534_submit_writer(port, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_err(&port->dev, "%s: submit failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return bytes_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static bool f81534_tx_empty(struct usb_serial_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct f81534_port_private *port_priv = usb_get_serial_port_data(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return test_bit(F81534_TX_EMPTY_BIT, &port_priv->tx_empty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int f81534_resume(struct usb_serial *serial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct f81534_serial_private *serial_priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) usb_get_serial_data(serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct usb_serial_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * We'll register port 0 bulkin when port had opened, It'll take all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * port received data, MSR register change and TX_EMPTY information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) mutex_lock(&serial_priv->urb_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (serial_priv->opened_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) status = f81534_submit_read_urb(serial, GFP_NOIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) mutex_unlock(&serial_priv->urb_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) mutex_unlock(&serial_priv->urb_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) for (i = 0; i < serial->num_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) port = serial->port[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (!tty_port_initialized(&port->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) status = f81534_submit_writer(port, GFP_NOIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dev_err(&port->dev, "%s: submit failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ++error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static struct usb_serial_driver f81534_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .name = "f81534",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .description = DRIVER_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .id_table = f81534_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .num_bulk_in = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .num_bulk_out = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .open = f81534_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .close = f81534_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .write = f81534_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .tx_empty = f81534_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .calc_num_ports = f81534_calc_num_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .port_probe = f81534_port_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .port_remove = f81534_port_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .break_ctl = f81534_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .dtr_rts = f81534_dtr_rts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .process_read_urb = f81534_process_read_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .get_serial = f81534_get_serial_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .tiocmget = f81534_tiocmget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .tiocmset = f81534_tiocmset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .write_bulk_callback = f81534_write_usb_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .set_termios = f81534_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .resume = f81534_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static struct usb_serial_driver *const serial_drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) &f81534_device, NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) module_usb_serial_driver(serial_drivers, f81534_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) MODULE_DEVICE_TABLE(usb, f81534_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) MODULE_AUTHOR("Peter Hong <Peter_Hong@fintek.com.tw>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) MODULE_AUTHOR("Tom Tsai <Tom_Tsai@fintek.com.tw>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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