Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas USB driver RZ/A initialization and power control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2018 Chris Brandt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2018-2019 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "rza.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static int usbhs_rza1_hardware_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	struct device_node *usb_x1_clk, *extal_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	u32 freq_usb = 0, freq_extal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	/* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	extal_clk = of_find_node_by_name(NULL, "extal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	of_property_read_u32(extal_clk, "clock-frequency", &freq_extal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	if (freq_usb == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		if (freq_extal == 12000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			/* Select 12MHz XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			usbhs_bset(priv, SYSCFG, UCKSEL, UCKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/* Enable USB PLL (NOTE: ch0 controls both ch0 and ch1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	usbhs_bset(priv, SYSCFG, UPLLE, UPLLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	usbhs_bset(priv, SUSPMODE, SUSPM, SUSPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const struct renesas_usbhs_platform_info usbhs_rza1_plat_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.platform_callback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		.hardware_init = usbhs_rza1_hardware_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		.get_id = usbhs_get_id_as_gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.driver_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		.has_new_pipe_configs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };