^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas USB driver R-Car Gen. 3 initialization and power control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-2019 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "rcar3.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LPSTS 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UGCTRL 0x180 /* 32-bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UGCTRL2 0x184 /* 32-bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define UGSTS 0x188 /* 32-bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Low Power Status register (LPSTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPSTS_SUSPM 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* R-Car D3 only: USB General control register (UGCTRL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UGCTRL_PLLRESET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UGCTRL_CONNECT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * USB General control register 2 (UGCTRL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Remarks: bit[31:11] and bit[9:6] should be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UGCTRL2_USB0SEL_HSUSB 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UGCTRL2_USB0SEL_OTG 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UGCTRL2_VBUSSEL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* R-Car D3 only: USB General status register (UGSTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UGSTS_LOCK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) iowrite32(data, priv->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return ioread32(priv->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *base, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* The controller on R-Car Gen3 needs to wait up to 45 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) usleep_range(45, 90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* R-Car D3 needs to release UGCTRL.PLLRESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *base, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) usbhs_rcar3_set_ugctrl2(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val = usbhs_read32(priv, UGSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } while (!(val & UGSTS_LOCK) && timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) usbhs_write32(priv, UGCTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct renesas_usbhs_platform_info usbhs_rcar_gen3_plat_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .platform_callback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .power_ctrl = usbhs_rcar3_power_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .get_id = usbhs_get_id_as_gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .driver_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .has_usb_dmac = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .multi_clks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .has_new_pipe_configs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct renesas_usbhs_platform_info usbhs_rcar_gen3_with_pll_plat_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .platform_callback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .power_ctrl = usbhs_rcar3_power_and_pll_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .get_id = usbhs_get_id_as_gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .driver_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .has_usb_dmac = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .multi_clks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .has_new_pipe_configs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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