Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-1.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Renesas USB driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2019 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef RENESAS_USB_DRIVER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define RENESAS_USB_DRIVER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/extcon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/usb/renesas_usbhs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct usbhs_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "mod.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "pipe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *		register define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SYSCFG		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define BUSWAIT		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DVSTCTR		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TESTMODE	0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CFIFO		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CFIFOSEL	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CFIFOCTR	0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define D0FIFO		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define D0FIFOSEL	0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define D0FIFOCTR	0x002A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define D1FIFO		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define D1FIFOSEL	0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define D1FIFOCTR	0x002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define INTENB0		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define INTENB1		0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BRDYENB		0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define NRDYENB		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define BEMPENB		0x003A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define INTSTS0		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define INTSTS1		0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BRDYSTS		0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define NRDYSTS		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BEMPSTS		0x004A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define FRMNUM		0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define USBREQ		0x0054	/* USB request type register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define USBVAL		0x0056	/* USB request value register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define USBINDX		0x0058	/* USB request index register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define USBLENG		0x005A	/* USB request length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DCPCFG		0x005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DCPMAXP		0x005E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DCPCTR		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PIPESEL		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PIPECFG		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PIPEBUF		0x006A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PIPEMAXP	0x006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PIPEPERI	0x006E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PIPEnCTR	0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PIPE1TRE	0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PIPE1TRN	0x0092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PIPE2TRE	0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PIPE2TRN	0x0096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PIPE3TRE	0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PIPE3TRN	0x009A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PIPE4TRE	0x009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PIPE4TRN	0x009E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PIPE5TRE	0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PIPE5TRN	0x00A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PIPEBTRE	0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PIPEBTRN	0x00A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PIPECTRE	0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PIPECTRN	0x00AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PIPEDTRE	0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PIPEDTRN	0x00AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PIPEETRE	0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PIPEETRN	0x00B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PIPEFTRE	0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PIPEFTRN	0x00B6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define PIPE9TRE	0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PIPE9TRN	0x00BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PIPEATRE	0x00BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PIPEATRN	0x00BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DEVADD0		0x00D0 /* Device address n configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DEVADD1		0x00D2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define DEVADD2		0x00D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DEVADD3		0x00D6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DEVADD4		0x00D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DEVADD5		0x00DA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DEVADD6		0x00DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DEVADD7		0x00DE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define DEVADD8		0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DEVADD9		0x00E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define DEVADDA		0x00E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define D2FIFOSEL	0x00F0	/* for R-Car Gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define D2FIFOCTR	0x00F2	/* for R-Car Gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define D3FIFOSEL	0x00F4	/* for R-Car Gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define D3FIFOCTR	0x00F6	/* for R-Car Gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SUSPMODE	0x0102	/* for RZ/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* SYSCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCKE	(1 << 10)	/* USB Module Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CNEN	(1 << 8)	/* Single-ended receiver operation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HSE	(1 << 7)	/* High-Speed Operation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DCFM	(1 << 6)	/* Controller Function Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRPD	(1 << 5)	/* D+ Line/D- Line Resistance Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DPRPU	(1 << 4)	/* D+ Line Resistance Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define USBE	(1 << 0)	/* USB Module Operation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UCKSEL	(1 << 2)	/* Clock Select for RZ/A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define UPLLE	(1 << 1)	/* USB PLL Enable for RZ/A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* DVSTCTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EXTLP	(1 << 10)	/* Controls the EXTLP pin output state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PWEN	(1 << 9)	/* Controls the PWEN pin output state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define USBRST	(1 << 6)	/* Bus Reset Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define UACT	(1 << 4)	/* USB Bus Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RHST	(0x7)		/* Reset Handshake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define  RHST_LOW_SPEED  1	/* Low-speed connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define  RHST_FULL_SPEED 2	/* Full-speed connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define  RHST_HIGH_SPEED 3	/* High-speed connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* CFIFOSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DREQE	(1 << 12)	/* DMA Transfer Request Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MBW_32	(0x2 << 10)	/* CFIFO Port Access Bit Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* CFIFOCTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BVAL	(1 << 15)	/* Buffer Memory Enable Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BCLR	(1 << 14)	/* CPU buffer clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FRDY	(1 << 13)	/* FIFO Port Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DTLN_MASK (0x0FFF)	/* Receive Data Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* INTENB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VBSE	(1 << 15)	/* Enable IRQ VBUS_0 and VBUSIN_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RSME	(1 << 14)	/* Enable IRQ Resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SOFE	(1 << 13)	/* Enable IRQ Frame Number Update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DVSE	(1 << 12)	/* Enable IRQ Device State Transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CTRE	(1 << 11)	/* Enable IRQ Control Stage Transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BEMPE	(1 << 10)	/* Enable IRQ Buffer Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define NRDYE	(1 << 9)	/* Enable IRQ Buffer Not Ready Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BRDYE	(1 << 8)	/* Enable IRQ Buffer Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* INTENB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BCHGE	(1 << 14)	/* USB Bus Change Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DTCHE	(1 << 12)	/* Disconnection Detect Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ATTCHE	(1 << 11)	/* Connection Detect Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EOFERRE	(1 << 6)	/* EOF Error Detect Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SIGNE	(1 << 5)	/* Setup Transaction Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SACKE	(1 << 4)	/* Setup Transaction ACK Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* INTSTS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VBINT	(1 << 15)	/* VBUS0_0 and VBUS1_0 Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DVST	(1 << 12)	/* Device State Transition Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CTRT	(1 << 11)	/* Control Stage Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BEMP	(1 << 10)	/* Buffer Empty Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BRDY	(1 << 8)	/* Buffer Ready Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VBSTS	(1 << 7)	/* VBUS_0 and VBUSIN_0 Input Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VALID	(1 << 3)	/* USB Request Receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DVSQ_MASK		(0x7 << 4)	/* Device State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define  POWER_STATE		(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define  DEFAULT_STATE		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define  ADDRESS_STATE		(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define  CONFIGURATION_STATE	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define  SUSPENDED_STATE	(4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CTSQ_MASK		(0x7)	/* Control Transfer Stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define  IDLE_SETUP_STAGE	0	/* Idle stage or setup stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define  READ_DATA_STAGE	1	/* Control read data stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define  READ_STATUS_STAGE	2	/* Control read status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define  WRITE_DATA_STAGE	3	/* Control write data stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define  WRITE_STATUS_STAGE	4	/* Control write status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define  NODATA_STATUS_STAGE	5	/* Control write NoData status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define  SEQUENCE_ERROR		6	/* Control transfer sequence error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* INTSTS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OVRCR	(1 << 15) /* OVRCR Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BCHG	(1 << 14) /* USB Bus Change Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DTCH	(1 << 12) /* USB Disconnection Detect Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ATTCH	(1 << 11) /* ATTCH Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EOFERR	(1 << 6)  /* EOF Error Detect Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SIGN	(1 << 5)  /* Setup Transaction Error Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SACK	(1 << 4)  /* Setup Transaction ACK Response Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* PIPECFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* DCPCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TYPE_NONE	(0 << 14)	/* Transfer Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TYPE_BULK	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TYPE_INT	(2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TYPE_ISO	(3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BFRE		(1 << 10)	/* BRDY Interrupt Operation Spec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DBLB		(1 << 9)	/* Double Buffer Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SHTNAK		(1 << 7)	/* Pipe Disable in Transfer End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DIR_OUT		(1 << 4)	/* Transfer Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* PIPEMAXP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* DCPMAXP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DEVSEL_MASK	(0xF << 12)	/* Device Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DCP_MAXP_MASK	(0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PIPE_MAXP_MASK	(0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* PIPEBUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BUFSIZE_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BUFSIZE_MASK	(0x1F << BUFSIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BUFNMB_MASK	(0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* PIPEnCTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* DCPCTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define BSTS		(1 << 15)	/* Buffer Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SUREQ		(1 << 14)	/* Sending SETUP Token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define INBUFM		(1 << 14)	/* (PIPEnCTR) Transfer Buffer Monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CSSTS		(1 << 12)	/* CSSTS Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define	ACLRM		(1 << 9)	/* Buffer Auto-Clear Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SQCLR		(1 << 8)	/* Toggle Bit Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SQSET		(1 << 7)	/* Toggle Bit Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SQMON		(1 << 6)	/* Toggle Bit Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PBUSY		(1 << 5)	/* Pipe Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PID_MASK	(0x3)		/* Response PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define  PID_NAK	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define  PID_BUF	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define  PID_STALL10	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define  PID_STALL11	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CCPL		(1 << 2)	/* Control Transfer End Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* PIPEnTRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TRENB		(1 << 9)	/* Transaction Counter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TRCLR		(1 << 8)	/* Transaction Counter Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* FRMNUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define FRNM_MASK	(0x7FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* DEVADDn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define UPPHUB(x)	(((x) & 0xF) << 11)	/* HUB Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HUBPORT(x)	(((x) & 0x7) << 8)	/* HUB Port for Target Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define USBSPD(x)	(((x) & 0x3) << 6)	/* Device Transfer Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define USBSPD_SPEED_LOW	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define USBSPD_SPEED_FULL	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define USBSPD_SPEED_HIGH	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* SUSPMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SUSPM		(1 << 14)	/* SuspendM Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  *		struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct usbhs_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	const struct renesas_usbhs_platform_callback *pfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct renesas_usbhs_driver_param	dparam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct delayed_work notify_hotplug_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	 * module control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct usbhs_mod_info mod_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 * pipe control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct usbhs_pipe_info pipe_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * fifo control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct usbhs_fifo_info fifo_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct reset_control *rsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct clk *clks[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int usbhs_get_id_as_gadget(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  * sysconfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * usb request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  * bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void usbhs_bus_send_reset(struct usbhs_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int usbhs_bus_get_speed(struct usbhs_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int usbhsc_schedule_notify_hotplug(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int usbhs_frame_get_num(struct usbhs_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  * device config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			   u16 hubport, u16 speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  * interrupt functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  * data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define usbhs_get_dparam(priv, param)	(priv->dparam.param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define usbhs_priv_to_pdev(priv)	(priv->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define usbhs_priv_to_dev(priv)		(&priv->pdev->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define usbhs_priv_to_lock(priv)	(&priv->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #endif /* RENESAS_USB_DRIVER_H */