^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __MV_USB_OTG_CONTROLLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __MV_USB_OTG_CONTROLLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Command Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define USBCMD_RUN_STOP (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define USBCMD_CTRL_RESET (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* otgsc Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OTGSC_CTRL_VUSB_CHARGE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OTGSC_CTRL_OTG_TERM 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OTGSC_CTRL_DATA_PULSING 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OTGSC_STS_USB_ID 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OTGSC_STS_A_VBUS_VALID 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OTGSC_STS_A_SESSION_VALID 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OTGSC_STS_B_SESSION_VALID 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OTGSC_STS_B_SESSION_END 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OTGSC_STS_1MS_TOGGLE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OTGSC_STS_DATA_PULSING 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OTGSC_INTSTS_USB_ID 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OTGSC_INTSTS_B_SESSION_END 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OTGSC_INTSTS_1MS 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OTGSC_INTSTS_DATA_PULSING 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OTGSC_INTR_USB_ID 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OTGSC_INTR_A_VBUS_VALID 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OTGSC_INTR_A_SESSION_VALID 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OTGSC_INTR_B_SESSION_VALID 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OTGSC_INTR_B_SESSION_END 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OTGSC_INTR_1MS_TIMER 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OTGSC_INTR_DATA_PULSING 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CAPLENGTH_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Timer's interval, unit 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define T_A_WAIT_VRISE 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define T_A_WAIT_BCON 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define T_A_AIDL_BDIS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define T_A_BIDL_ADIS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define T_B_ASE0_BRST 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define T_B_SE0_SRP 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define T_B_SRP_FAIL 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define T_B_DATA_PLS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define T_B_SRP_INIT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define T_A_SRP_RSPNS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define T_A_DRV_RSM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum otg_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) OTG_B_DEVICE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) OTG_A_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum mv_otg_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) A_WAIT_BCON_TIMER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OTG_TIMER_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* PXA OTG state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct mv_otg_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* internal variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 b_srp_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 b_hnp_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* OTG inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 a_bus_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 a_bus_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 a_clr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 a_bus_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 a_bus_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 a_conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 a_sess_vld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 a_srp_det;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 a_vbus_vld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 b_bus_req; /* B-Device Require Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 b_bus_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 b_bus_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 b_conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 b_se0_srp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 b_sess_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 b_sess_vld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 a_suspend_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*Timer event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 a_aidl_bdis_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 b_ase0_brst_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 a_bidl_adis_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 a_wait_bcon_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct timer_list timer[OTG_TIMER_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VUSBHS_MAX_PORTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mv_otg_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 usbcmd; /* Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 usbsts; /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 usbintr; /* Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 frindex; /* Frame index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 reserved1[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 deviceaddr; /* Device Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 eplistaddr; /* Endpoint List Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 ttctrl; /* HOST TT status and control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 burstsize; /* Programmable Burst Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 epnak; /* Endpoint NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 epnaken; /* Endpoint NAK Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 configflag; /* Configured Flag register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 otgsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 usbmode; /* USB Host/Device mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 epsetupstat; /* Endpoint Setup Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 epprime; /* Endpoint Initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 epflush; /* Endpoint De-initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 epstatus; /* Endpoint Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 epcomplete; /* Endpoint Interrupt On Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 mcr; /* Mux Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 isr; /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 ier; /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mv_otg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct usb_phy phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mv_otg_ctrl otg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void __iomem *phy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void __iomem *cap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct mv_otg_regs __iomem *op_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct workqueue_struct *qwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) spinlock_t wq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct mv_usb_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int clock_gating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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