^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chao Xie <chao.xie@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Neil Zhang <zhangwm@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/mv_usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "phy-mv-usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRIVER_DESC "Marvell USB OTG transceiver driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char driver_name[] = "mv-otg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static char *state_string[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "undefined",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "b_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "b_srp_init",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "b_peripheral",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "b_wait_acon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "b_host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "a_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "a_wait_vrise",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "a_wait_bcon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "a_host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "a_suspend",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "a_peripheral",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "a_wait_vfall",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "a_vbus_err"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int mv_otg_set_vbus(struct usb_otg *otg, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct mv_otg *mvotg = container_of(otg->usb_phy, struct mv_otg, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (mvotg->pdata->set_vbus == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return mvotg->pdata->set_vbus(on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int mv_otg_set_host(struct usb_otg *otg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct usb_bus *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) otg->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int mv_otg_set_peripheral(struct usb_otg *otg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) otg->gadget = gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void mv_otg_run_state_machine(struct mv_otg *mvotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_dbg(&mvotg->pdev->dev, "transceiver is updated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!mvotg->qwork)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) queue_delayed_work(mvotg->qwork, &mvotg->work, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void mv_otg_timer_await_bcon(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mv_otg *mvotg = from_timer(mvotg, t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) otg_ctrl.timer[A_WAIT_BCON_TIMER]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mvotg->otg_ctrl.a_wait_bcon_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_info(&mvotg->pdev->dev, "B Device No Response!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (spin_trylock(&mvotg->wq_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mv_otg_run_state_machine(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_unlock(&mvotg->wq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int mv_otg_cancel_timer(struct mv_otg *mvotg, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct timer_list *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (id >= OTG_TIMER_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) timer = &mvotg->otg_ctrl.timer[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (timer_pending(timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) del_timer(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int mv_otg_set_timer(struct mv_otg *mvotg, unsigned int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct timer_list *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (id >= OTG_TIMER_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) timer = &mvotg->otg_ctrl.timer[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (timer_pending(timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_err(&mvotg->pdev->dev, "Timer%d is already running\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) timer->expires = jiffies + interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) add_timer(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int mv_otg_reset(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Stop the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) tmp = readl(&mvotg->op_regs->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tmp &= ~USBCMD_RUN_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(tmp, &mvotg->op_regs->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Reset the controller to get default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = readl_poll_timeout_atomic(&mvotg->op_regs->usbcmd, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (tmp & USBCMD_CTRL_RESET), 10, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(&mvotg->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "Wait for RESET completed TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(0x0, &mvotg->op_regs->usbintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) tmp = readl(&mvotg->op_regs->usbsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel(tmp, &mvotg->op_regs->usbsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void mv_otg_init_irq(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 otgsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mvotg->irq_en = OTGSC_INTR_A_SESSION_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) | OTGSC_INTR_A_VBUS_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mvotg->irq_status = OTGSC_INTSTS_A_SESSION_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) | OTGSC_INTSTS_A_VBUS_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (mvotg->pdata->vbus == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mvotg->irq_en |= OTGSC_INTR_B_SESSION_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) | OTGSC_INTR_B_SESSION_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mvotg->irq_status |= OTGSC_INTSTS_B_SESSION_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) | OTGSC_INTSTS_B_SESSION_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (mvotg->pdata->id == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mvotg->irq_en |= OTGSC_INTR_USB_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mvotg->irq_status |= OTGSC_INTSTS_USB_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) otgsc = readl(&mvotg->op_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) otgsc |= mvotg->irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(otgsc, &mvotg->op_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void mv_otg_start_host(struct mv_otg *mvotg, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #ifdef CONFIG_USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct usb_otg *otg = mvotg->phy.otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!otg->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_info(&mvotg->pdev->dev, "%s host\n", on ? "start" : "stop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) hcd = bus_to_hcd(otg->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) device_wakeup_enable(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif /* CONFIG_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void mv_otg_start_periphrals(struct mv_otg *mvotg, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct usb_otg *otg = mvotg->phy.otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!otg->gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_info(mvotg->phy.dev, "gadget %s\n", on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) usb_gadget_vbus_connect(otg->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) usb_gadget_vbus_disconnect(otg->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void otg_clock_enable(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) clk_prepare_enable(mvotg->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void otg_clock_disable(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clk_disable_unprepare(mvotg->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int mv_otg_enable_internal(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (mvotg->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) otg_clock_enable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (mvotg->pdata->phy_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) retval = mvotg->pdata->phy_init(mvotg->phy_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_err(&mvotg->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "init phy error %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) otg_clock_disable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mvotg->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int mv_otg_enable(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (mvotg->clock_gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return mv_otg_enable_internal(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void mv_otg_disable_internal(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (mvotg->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (mvotg->pdata->phy_deinit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mvotg->pdata->phy_deinit(mvotg->phy_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) otg_clock_disable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mvotg->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void mv_otg_disable(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (mvotg->clock_gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mv_otg_disable_internal(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void mv_otg_update_inputs(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 otgsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) otgsc = readl(&mvotg->op_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (mvotg->pdata->vbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (mvotg->pdata->vbus->poll() == VBUS_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) otg_ctrl->b_sess_vld = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) otg_ctrl->b_sess_end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) otg_ctrl->b_sess_vld = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) otg_ctrl->b_sess_end = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) otg_ctrl->b_sess_vld = !!(otgsc & OTGSC_STS_B_SESSION_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) otg_ctrl->b_sess_end = !!(otgsc & OTGSC_STS_B_SESSION_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (mvotg->pdata->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) otg_ctrl->id = !!mvotg->pdata->id->poll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) otg_ctrl->id = !!(otgsc & OTGSC_STS_USB_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (mvotg->pdata->otg_force_a_bus_req && !otg_ctrl->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) otg_ctrl->a_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) otg_ctrl->a_sess_vld = !!(otgsc & OTGSC_STS_A_SESSION_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) otg_ctrl->a_vbus_vld = !!(otgsc & OTGSC_STS_A_VBUS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_dbg(&mvotg->pdev->dev, "%s: ", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_dbg(&mvotg->pdev->dev, "id %d\n", otg_ctrl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_dbg(&mvotg->pdev->dev, "b_sess_vld %d\n", otg_ctrl->b_sess_vld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_dbg(&mvotg->pdev->dev, "b_sess_end %d\n", otg_ctrl->b_sess_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_dbg(&mvotg->pdev->dev, "a_vbus_vld %d\n", otg_ctrl->a_vbus_vld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(&mvotg->pdev->dev, "a_sess_vld %d\n", otg_ctrl->a_sess_vld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void mv_otg_update_state(struct mv_otg *mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int old_state = mvotg->phy.otg->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) switch (old_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case OTG_STATE_UNDEFINED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mvotg->phy.otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case OTG_STATE_B_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (otg_ctrl->id == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mvotg->phy.otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else if (otg_ctrl->b_sess_vld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mvotg->phy.otg->state = OTG_STATE_B_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case OTG_STATE_B_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mvotg->phy.otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case OTG_STATE_A_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (otg_ctrl->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mvotg->phy.otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else if (!(otg_ctrl->a_bus_drop) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mvotg->phy.otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case OTG_STATE_A_WAIT_VRISE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (otg_ctrl->a_vbus_vld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mvotg->phy.otg->state = OTG_STATE_A_WAIT_BCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (otg_ctrl->id || otg_ctrl->a_bus_drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) || otg_ctrl->a_wait_bcon_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mvotg->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) otg_ctrl->a_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else if (!otg_ctrl->a_vbus_vld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mvotg->phy.otg->state = OTG_STATE_A_VBUS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else if (otg_ctrl->b_conn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mvotg->phy.otg->state = OTG_STATE_A_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case OTG_STATE_A_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (otg_ctrl->id || !otg_ctrl->b_conn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) || otg_ctrl->a_bus_drop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mvotg->phy.otg->state = OTG_STATE_A_WAIT_BCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) else if (!otg_ctrl->a_vbus_vld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mvotg->phy.otg->state = OTG_STATE_A_VBUS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case OTG_STATE_A_WAIT_VFALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (otg_ctrl->id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) || otg_ctrl->a_bus_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mvotg->phy.otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case OTG_STATE_A_VBUS_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (otg_ctrl->id || otg_ctrl->a_clr_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) || otg_ctrl->a_bus_drop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) otg_ctrl->a_clr_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mvotg->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void mv_otg_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct mv_otg *mvotg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct usb_otg *otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int old_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mvotg = container_of(to_delayed_work(work), struct mv_otg, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) run:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* work queue is single thread, or we need spin_lock to protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) otg = mvotg->phy.otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) old_state = otg->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!mvotg->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mv_otg_update_inputs(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mv_otg_update_state(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (old_state != mvotg->phy.otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) state_string[old_state],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) state_string[mvotg->phy.otg->state]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch (mvotg->phy.otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case OTG_STATE_B_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) otg->default_a = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (old_state == OTG_STATE_B_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mv_otg_start_periphrals(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mv_otg_reset(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mv_otg_disable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) usb_phy_set_event(&mvotg->phy, USB_EVENT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case OTG_STATE_B_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mv_otg_enable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mv_otg_start_periphrals(mvotg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) usb_phy_set_event(&mvotg->phy, USB_EVENT_ENUMERATED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case OTG_STATE_A_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) otg->default_a = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mv_otg_enable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (old_state == OTG_STATE_A_WAIT_VFALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mv_otg_start_host(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mv_otg_reset(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case OTG_STATE_A_WAIT_VRISE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mv_otg_set_vbus(otg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (old_state != OTG_STATE_A_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mv_otg_start_host(mvotg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mv_otg_set_timer(mvotg, A_WAIT_BCON_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) T_A_WAIT_BCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Now, we directly enter A_HOST. So set b_conn = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * here. In fact, it need host driver to notify us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mvotg->otg_ctrl.b_conn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case OTG_STATE_A_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case OTG_STATE_A_WAIT_VFALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Now, we has exited A_HOST. So set b_conn = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * here. In fact, it need host driver to notify us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mvotg->otg_ctrl.b_conn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mv_otg_set_vbus(otg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case OTG_STATE_A_VBUS_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto run;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static irqreturn_t mv_otg_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct mv_otg *mvotg = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 otgsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) otgsc = readl(&mvotg->op_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) writel(otgsc, &mvotg->op_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * if we have vbus, then the vbus detection for B-device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * will be done by mv_otg_inputs_irq().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (mvotg->pdata->vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if ((otgsc & OTGSC_STS_USB_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) !(otgsc & OTGSC_INTSTS_USB_ID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if ((otgsc & mvotg->irq_status) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mv_otg_run_state_machine(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static irqreturn_t mv_otg_inputs_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct mv_otg *mvotg = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* The clock may disabled at this time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (!mvotg->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) mv_otg_enable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mv_otg_init_irq(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mv_otg_run_state_machine(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) a_bus_req_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct mv_otg *mvotg = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return scnprintf(buf, PAGE_SIZE, "%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mvotg->otg_ctrl.a_bus_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) a_bus_req_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct mv_otg *mvotg = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* We will use this interface to change to A device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (mvotg->phy.otg->state != OTG_STATE_B_IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) && mvotg->phy.otg->state != OTG_STATE_A_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* The clock may disabled and we need to set irq for ID detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mv_otg_enable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mv_otg_init_irq(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (buf[0] == '1') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mvotg->otg_ctrl.a_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mvotg->otg_ctrl.a_bus_drop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_dbg(&mvotg->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "User request: a_bus_req = 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (spin_trylock(&mvotg->wq_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mv_otg_run_state_machine(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spin_unlock(&mvotg->wq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static DEVICE_ATTR_RW(a_bus_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) a_clr_err_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct mv_otg *mvotg = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!mvotg->phy.otg->default_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (buf[0] == '1') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mvotg->otg_ctrl.a_clr_err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_dbg(&mvotg->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "User request: a_clr_err = 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (spin_trylock(&mvotg->wq_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mv_otg_run_state_machine(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) spin_unlock(&mvotg->wq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static DEVICE_ATTR_WO(a_clr_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) a_bus_drop_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct mv_otg *mvotg = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return scnprintf(buf, PAGE_SIZE, "%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mvotg->otg_ctrl.a_bus_drop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) a_bus_drop_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct mv_otg *mvotg = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!mvotg->phy.otg->default_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (buf[0] == '0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mvotg->otg_ctrl.a_bus_drop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_dbg(&mvotg->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "User request: a_bus_drop = 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } else if (buf[0] == '1') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mvotg->otg_ctrl.a_bus_drop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mvotg->otg_ctrl.a_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_dbg(&mvotg->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "User request: a_bus_drop = 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_dbg(&mvotg->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "User request: and a_bus_req = 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (spin_trylock(&mvotg->wq_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mv_otg_run_state_machine(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) spin_unlock(&mvotg->wq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static DEVICE_ATTR_RW(a_bus_drop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct attribute *inputs_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &dev_attr_a_bus_req.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) &dev_attr_a_clr_err.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) &dev_attr_a_bus_drop.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const struct attribute_group inputs_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = "inputs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .attrs = inputs_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct attribute_group *mv_otg_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &inputs_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int mv_otg_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct mv_otg *mvotg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (mvotg->qwork) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) flush_workqueue(mvotg->qwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) destroy_workqueue(mvotg->qwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mv_otg_disable(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) usb_remove_phy(&mvotg->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int mv_otg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct mv_usb_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct mv_otg *mvotg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct usb_otg *otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int retval = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_err(&pdev->dev, "failed to get platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mvotg = devm_kzalloc(&pdev->dev, sizeof(*mvotg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!mvotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) platform_set_drvdata(pdev, mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mvotg->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mvotg->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mvotg->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (IS_ERR(mvotg->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return PTR_ERR(mvotg->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mvotg->qwork = create_singlethread_workqueue("mv_otg_queue");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (!mvotg->qwork) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) INIT_DELAYED_WORK(&mvotg->work, mv_otg_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* OTG common part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) mvotg->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) mvotg->phy.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mvotg->phy.otg = otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) mvotg->phy.label = driver_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) otg->state = OTG_STATE_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) otg->usb_phy = &mvotg->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) otg->set_host = mv_otg_set_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) otg->set_peripheral = mv_otg_set_peripheral;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) otg->set_vbus = mv_otg_set_vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) for (i = 0; i < OTG_TIMER_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) timer_setup(&mvotg->otg_ctrl.timer[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) mv_otg_timer_await_bcon, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) r = platform_get_resource_byname(mvotg->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) IORESOURCE_MEM, "phyregs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (r == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) goto err_destroy_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mvotg->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (mvotg->phy_regs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_err(&pdev->dev, "failed to map phy I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) retval = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) goto err_destroy_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) r = platform_get_resource_byname(mvotg->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) IORESOURCE_MEM, "capregs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (r == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(&pdev->dev, "no I/O memory resource defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) goto err_destroy_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mvotg->cap_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (mvotg->cap_regs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_err(&pdev->dev, "failed to map I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) retval = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) goto err_destroy_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* we will acces controller register, so enable the udc controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) retval = mv_otg_enable_internal(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_err(&pdev->dev, "mv otg enable error %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) goto err_destroy_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mvotg->op_regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) + (readl(mvotg->cap_regs) & CAPLENGTH_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (pdata->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) retval = devm_request_threaded_irq(&pdev->dev, pdata->id->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) NULL, mv_otg_inputs_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) IRQF_ONESHOT, "id", mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "Failed to request irq for ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pdata->id = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (pdata->vbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mvotg->clock_gating = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) retval = devm_request_threaded_irq(&pdev->dev, pdata->vbus->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) NULL, mv_otg_inputs_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) IRQF_ONESHOT, "vbus", mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "Failed to request irq for VBUS, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "disable clock gating\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mvotg->clock_gating = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pdata->vbus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (pdata->disable_otg_clock_gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mvotg->clock_gating = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mv_otg_reset(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mv_otg_init_irq(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (r == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_err(&pdev->dev, "no IRQ resource defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mvotg->irq = r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (devm_request_irq(&pdev->dev, mvotg->irq, mv_otg_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) driver_name, mvotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev_err(&pdev->dev, "Request irq %d for OTG failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) mvotg->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mvotg->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) retval = usb_add_phy(&mvotg->phy, USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_err(&pdev->dev, "can't register transceiver, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) spin_lock_init(&mvotg->wq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (spin_trylock(&mvotg->wq_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mv_otg_run_state_machine(mvotg, 2 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) spin_unlock(&mvotg->wq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "successful probe OTG device %s clock gating.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mvotg->clock_gating ? "with" : "without");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mv_otg_disable_internal(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) err_destroy_workqueue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) flush_workqueue(mvotg->qwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) destroy_workqueue(mvotg->qwork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct mv_otg *mvotg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (mvotg->phy.otg->state != OTG_STATE_B_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "OTG state is not B_IDLE, it is %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) mvotg->phy.otg->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!mvotg->clock_gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) mv_otg_disable_internal(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int mv_otg_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct mv_otg *mvotg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u32 otgsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!mvotg->clock_gating) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) mv_otg_enable_internal(mvotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) otgsc = readl(&mvotg->op_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) otgsc |= mvotg->irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) writel(otgsc, &mvotg->op_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (spin_trylock(&mvotg->wq_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mv_otg_run_state_machine(mvotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) spin_unlock(&mvotg->wq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static struct platform_driver mv_otg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .probe = mv_otg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .remove = mv_otg_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .name = driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .dev_groups = mv_otg_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .suspend = mv_otg_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .resume = mv_otg_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) module_platform_driver(mv_otg_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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