^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/usb/otg-fsm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* USB Command Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define USB_CMD_RUN_STOP (0x1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define USB_CMD_CTRL_RESET (0x1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define USB_CMD_INT_AA_DOORBELL (0x1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define USB_CMD_ASP (0x3<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define USB_CMD_SUTW (0x1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define USB_CMD_ATDTW (0x1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define USB_CMD_ITC (0xFF<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* bit 15,3,2 are frame list size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* bit 9-8 are async schedule park mode count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USB_CMD_ASP_00 (0x0<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define USB_CMD_ASP_01 (0x1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USB_CMD_ASP_10 (0x2<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USB_CMD_ASP_11 (0x3<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define USB_CMD_ASP_BIT_POS (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* bit 23-16 are interrupt threshold control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define USB_CMD_ITC_NO_THRESHOLD (0x00<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USB_CMD_ITC_1_MICRO_FRM (0x01<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USB_CMD_ITC_2_MICRO_FRM (0x02<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USB_CMD_ITC_4_MICRO_FRM (0x04<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USB_CMD_ITC_8_MICRO_FRM (0x08<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USB_CMD_ITC_16_MICRO_FRM (0x10<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define USB_CMD_ITC_32_MICRO_FRM (0x20<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USB_CMD_ITC_64_MICRO_FRM (0x40<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USB_CMD_ITC_BIT_POS (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* USB Status Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB_STS_INT (0x1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USB_STS_ERR (0x1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USB_STS_PORT_CHANGE (0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USB_STS_FRM_LST_ROLL (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USB_STS_SYS_ERR (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USB_STS_IAA (0x1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USB_STS_RESET_RECEIVED (0x1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define USB_STS_SOF (0x1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define USB_STS_DCSUSPEND (0x1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USB_STS_HC_HALTED (0x1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USB_STS_RCL (0x1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USB_STS_PERIODIC_SCHEDULE (0x1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USB_STS_ASYNC_SCHEDULE (0x1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* USB Interrupt Enable Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define USB_INTR_INT_EN (0x1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define USB_INTR_ERR_INT_EN (0x1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define USB_INTR_PC_DETECT_EN (0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USB_INTR_FRM_LST_ROLL_EN (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USB_INTR_SYS_ERR_EN (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define USB_INTR_ASYN_ADV_EN (0x1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define USB_INTR_RESET_EN (0x1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define USB_INTR_SOF_EN (0x1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define USB_INTR_DEVICE_SUSPEND (0x1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Device Address bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define USB_DEVICE_ADDRESS_MASK (0x7F<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define USB_DEVICE_ADDRESS_BIT_POS (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* PORTSC Register Bit Masks,Only one PORT in OTG mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PORTSC_PORT_ENABLE (0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PORTSC_OVER_CURRENT_ACT (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PORTSC_OVER_CUURENT_CHG (0x1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PORTSC_PORT_FORCE_RESUME (0x1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PORTSC_PORT_SUSPEND (0x1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PORTSC_PORT_RESET (0x1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PORTSC_LINE_STATUS_BITS (0x3<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PORTSC_PORT_POWER (0x1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PORTSC_PORT_INDICTOR_CTRL (0x3<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PORTSC_PORT_TEST_CTRL (0xF<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PORTSC_PHY_LOW_POWER_SPD (0x1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PORTSC_PORT_SPEED_MASK (0x3<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PORTSC_TRANSCEIVER_WIDTH (0x1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PORTSC_PHY_TYPE_SEL (0x3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* bit 11-10 are line status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PORTSC_LINE_STATUS_SE0 (0x0<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PORTSC_LINE_STATUS_JSTATE (0x1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PORTSC_LINE_STATUS_KSTATE (0x2<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PORTSC_LINE_STATUS_UNDEF (0x3<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PORTSC_LINE_STATUS_BIT_POS (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* bit 15-14 are port indicator control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PORTSC_PIC_OFF (0x0<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PORTSC_PIC_AMBER (0x1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PORTSC_PIC_GREEN (0x2<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PORTSC_PIC_UNDEF (0x3<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PORTSC_PIC_BIT_POS (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* bit 19-16 are port test control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PORTSC_PTC_DISABLE (0x0<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PORTSC_PTC_JSTATE (0x1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PORTSC_PTC_KSTATE (0x2<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PORTSC_PTC_SEQNAK (0x3<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PORTSC_PTC_PACKET (0x4<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PORTSC_PTC_FORCE_EN (0x5<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PORTSC_PTC_BIT_POS (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* bit 27-26 are port speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PORTSC_PORT_SPEED_FULL (0x0<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PORTSC_PORT_SPEED_LOW (0x1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PORTSC_PORT_SPEED_HIGH (0x2<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PORTSC_PORT_SPEED_UNDEF (0x3<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PORTSC_SPEED_BIT_POS (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* bit 28 is parallel transceiver width for UTMI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PORTSC_PTW (0x1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PORTSC_PTW_8BIT (0x0<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PORTSC_PTW_16BIT (0x1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* bit 31-30 are port transceiver select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PORTSC_PTS_UTMI (0x0<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PORTSC_PTS_ULPI (0x2<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PORTSC_PTS_FSLS_SERIAL (0x3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PORTSC_PTS_BIT_POS (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PORTSC_W1C_BITS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (PORTSC_CONNECT_STATUS_CHANGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PORTSC_PORT_EN_DIS_CHANGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PORTSC_OVER_CUURENT_CHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* OTG Status Control Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OTGSC_CTRL_VBUS_CHARGE (0x1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OTGSC_CTRL_OTG_TERMINATION (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OTGSC_CTRL_DATA_PULSING (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OTGSC_CTRL_ID_PULL_EN (0x1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OTGSC_HA_DATA_PULSE (0x1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OTGSC_HA_BA (0x1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OTGSC_STS_USB_ID (0x1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OTGSC_STS_A_VBUS_VALID (0x1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OTGSC_STS_A_SESSION_VALID (0x1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OTGSC_STS_B_SESSION_VALID (0x1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OTGSC_STS_B_SESSION_END (0x1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OTGSC_STS_1MS_TOGGLE (0x1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OTGSC_STS_DATA_PULSING (0x1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OTGSC_INTSTS_USB_ID (0x1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OTGSC_INTSTS_B_SESSION_END (0x1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OTGSC_INTSTS_1MS (0x1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OTGSC_INTSTS_DATA_PULSING (0x1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OTGSC_INTR_USB_ID_EN (0x1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OTGSC_INTR_B_SESSION_END_EN (0x1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OTGSC_INTR_1MS_TIMER_EN (0x1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OTGSC_INTR_DATA_PULSING_EN (0x1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OTGSC_INTSTS_MASK (0x00ff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* USB MODE Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define USB_MODE_CTRL_MODE_IDLE (0x0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define USB_MODE_CTRL_MODE_DEVICE (0x2<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define USB_MODE_CTRL_MODE_HOST (0x3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define USB_MODE_CTRL_MODE_RSV (0x1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define USB_MODE_SETUP_LOCK_OFF (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define USB_MODE_STREAM_DISABLE (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define USB_MODE_ES (0x1<<2) /* Endian Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* control Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define USB_CTRL_IOENB (0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define USB_CTRL_ULPI_INT0EN (0x1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* BCSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BCSR5_INT_USB (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* USB module clk cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SCCR_OFFS (0xA08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SCCR_USB_MPHCM_11 (0x00c00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SCCR_USB_MPHCM_01 (0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SCCR_USB_MPHCM_10 (0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SCCR_USB_DRCM_11 (0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SCCR_USB_DRCM_01 (0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SCCR_USB_DRCM_10 (0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SICRL_OFFS (0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SICRL_USB0 (0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SICRL_USB1 (0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SICRH_OFFS (0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SICRH_USB_UTMI (0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* OTG interrupt enable bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OTGSC_INTERRUPT_ENABLE_BITS_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (OTGSC_INTR_USB_ID_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) OTGSC_INTR_1MS_TIMER_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) OTGSC_INTR_A_VBUS_VALID_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) OTGSC_INTR_A_SESSION_VALID_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) OTGSC_INTR_B_SESSION_VALID_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) OTGSC_INTR_B_SESSION_END_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) OTGSC_INTR_DATA_PULSING_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* OTG interrupt status bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OTGSC_INTERRUPT_STATUS_BITS_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (OTGSC_INTSTS_USB_ID | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) OTGSC_INTR_1MS_TIMER_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) OTGSC_INTSTS_A_VBUS_VALID | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) OTGSC_INTSTS_A_SESSION_VALID | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) OTGSC_INTSTS_B_SESSION_VALID | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) OTGSC_INTSTS_B_SESSION_END | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) OTGSC_INTSTS_DATA_PULSING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * A-DEVICE timing constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Wait for VBUS Rise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Wait for B-Connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * This is only used to get out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * OTG_STATE_A_WAIT_BCON state if there was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * no connection for these many milliseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* A-Idle to B-Disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* It is necessary for this timer to be more than 750 ms because of a bug in OPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * in the test description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* B-Idle to A-Disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TA_BIDL_ADIS (12) /* 3 to 200 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* B-device timing constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Data-Line Pulse Time*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TB_DATA_PLS_MAX (10) /* maximum 10 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* SRP Initiate Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* SRP Fail Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* SRP result wait time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TB_SRP_WAIT (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* VBus time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Discharge time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* This time should be less than 10ms. It varies from system to system. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TB_VBUS_DSCHRG (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* A-SE0 to B-Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* A bus suspend timer before we can switch to b_wait_aconn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TB_A_SUSPEND (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TB_BUS_RESUME (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* SE0 Time Before SRP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SET_OTG_STATE(phy, newstate) ((phy)->otg->state = newstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct usb_dr_mmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Capability register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 res1[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u16 caplength; /* Capability Register Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u16 hciversion; /* Host Controller Interface Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 hcsparams; /* Host Controller Structual Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 hccparams; /* Host Controller Capability Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 res2[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 dciversion; /* Device Controller Interface Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 dccparams; /* Device Controller Capability Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 res3[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Operation register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 usbcmd; /* USB Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 usbsts; /* USB Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 usbintr; /* USB Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 frindex; /* Frame Index Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 res4[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 deviceaddr; /* Device Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 endpointlistaddr; /* Endpoint List Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 res5[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 burstsize; /* Master Interface Data Burst Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 res6[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 ulpiview; /* ULPI register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 res7[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 configflag; /* Configure Flag Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 portsc; /* Port 1 Status and Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 res8[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 otgsc; /* On-The-Go Status and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 usbmode; /* USB Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 endptsetupstat; /* Endpoint Setup Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 endpointprime; /* Endpoint Initialization Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 endptflush; /* Endpoint Flush Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 endptstatus; /* Endpoint Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 endptcomplete; /* Endpoint Complete Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 endptctrl[6]; /* Endpoint Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 res9[552];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 snoop1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 snoop2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 age_cnt_thresh; /* Age Count Threshold Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 pri_ctrl; /* Priority Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 si_ctrl; /* System Interface Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 res10[236];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 control; /* General Purpose Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct fsl_otg_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned long expires; /* Number of count increase to timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned long count; /* Tick counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void (*function)(unsigned long); /* Timeout function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long data; /* Data passed to function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) inline struct fsl_otg_timer *otg_timer_initializer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) (void (*function)(unsigned long), unsigned long expires, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct fsl_otg_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) timer->function = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) timer->expires = expires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) timer->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct fsl_otg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct usb_phy phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct otg_fsm fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct usb_dr_mmap *dr_mem_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct delayed_work otg_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* used for usb host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct work_struct work_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 host_working;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct fsl_otg_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 otg_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define FSL_OTG_NAME "fsl-usb2-otg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void fsl_otg_add_timer(struct otg_fsm *fsm, void *timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) void fsl_otg_del_timer(struct otg_fsm *fsm, void *timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void fsl_otg_pulse_vbus(void);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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