^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Li Yang <LeoLi@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jerry Huang <Chang-Ming.Huang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Initialization based on code from Shlomi Gridish.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/fsl_devices.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "phy-fsl-usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifdef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VDBG(fmt, args...) pr_debug("[%s] " fmt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __func__, ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VDBG(stuff...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRIVER_VERSION "Rev. 1.55"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRIVER_AUTHOR "Jerry Huang/Li Yang"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRIVER_DESC "Freescale USB OTG Transceiver Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char driver_name[] = "fsl-usb2-otg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const pm_message_t otg_suspend_state = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .event = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HA_DATA_PULSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct usb_dr_mmap *usb_dr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct fsl_otg *fsl_otg_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int srp_wait_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* FSM timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *b_ase0_brst_tmr, *b_se0_srp_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Driver specific timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *b_srp_wait_tmr, *a_wait_enum_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct list_head active_timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct fsl_otg_config fsl_otg_initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .otg_port = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static u32 _fsl_readl_be(const unsigned __iomem *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return in_be32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static u32 _fsl_readl_le(const unsigned __iomem *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return in_le32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void _fsl_writel_be(u32 v, unsigned __iomem *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) out_be32(p, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void _fsl_writel_le(u32 v, unsigned __iomem *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) out_le32(p, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static u32 (*_fsl_readl)(const unsigned __iomem *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define fsl_readl(p) (*_fsl_readl)((p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define fsl_readl(addr) readl(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define fsl_writel(val, addr) writel(val, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* CONFIG_PPC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int write_ulpi(u8 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) temp = 0x60000000 | (addr << 16) | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) fsl_writel(temp, &usb_dr_regs->ulpiview);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* -------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Operations that will be called from OTG Finite State Machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Charge vbus for vbus pulsing in SRP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void fsl_otg_chrg_vbus(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* stop discharging, start charging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) OTGSC_CTRL_VBUS_CHARGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* stop charging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) fsl_writel(tmp, &usb_dr_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Discharge vbus through a resistor to ground */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void fsl_otg_dischrg_vbus(int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* stop charging, start discharging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) OTGSC_CTRL_VBUS_DISCHARGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* stop discharging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) fsl_writel(tmp, &usb_dr_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* A-device driver vbus, controlled through PP bit in PORTSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void fsl_otg_drv_vbus(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tmp = fsl_readl(&usb_dr_regs->portsc) & ~PORTSC_W1C_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) fsl_writel(tmp | PORTSC_PORT_POWER, &usb_dr_regs->portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tmp = fsl_readl(&usb_dr_regs->portsc) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) fsl_writel(tmp, &usb_dr_regs->portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Pull-up D+, signalling connect by periperal. Also used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * data-line pulsing in SRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void fsl_otg_loc_conn(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tmp |= OTGSC_CTRL_DATA_PULSING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tmp &= ~OTGSC_CTRL_DATA_PULSING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) fsl_writel(tmp, &usb_dr_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Generate SOF by host. This is controlled through suspend/resume the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * port. In host mode, controller will automatically send SOF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Suspend will block the data on the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void fsl_otg_loc_sof(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) tmp |= PORTSC_PORT_FORCE_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tmp |= PORTSC_PORT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void fsl_otg_start_pulse(struct otg_fsm *fsm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) srp_wait_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef HA_DATA_PULSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tmp |= OTGSC_HA_DATA_PULSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) fsl_writel(tmp, &usb_dr_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) fsl_otg_loc_conn(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) fsl_otg_add_timer(fsm, b_data_pulse_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void b_data_pulse_end(unsigned long foo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #ifdef HA_DATA_PULSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) fsl_otg_loc_conn(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Do VBUS pulse after data pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) fsl_otg_pulse_vbus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void fsl_otg_pulse_vbus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) srp_wait_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fsl_otg_chrg_vbus(&fsl_otg_dev->fsm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* start the timer to end vbus charge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) fsl_otg_add_timer(&fsl_otg_dev->fsm, b_vbus_pulse_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void b_vbus_pulse_end(unsigned long foo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) fsl_otg_chrg_vbus(&fsl_otg_dev->fsm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * As USB3300 using the same a_sess_vld and b_sess_vld voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * we need to discharge the bus for a while to distinguish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * residual voltage of vbus pulsing and A device pull up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) fsl_otg_dischrg_vbus(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) fsl_otg_add_timer(&fsl_otg_dev->fsm, b_srp_wait_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void b_srp_end(unsigned long foo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) fsl_otg_dischrg_vbus(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) srp_wait_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if ((fsl_otg_dev->phy.otg->state == OTG_STATE_B_SRP_INIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) fsl_otg_dev->fsm.b_sess_vld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) fsl_otg_dev->fsm.b_srp_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Workaround for a_host suspending too fast. When a_bus_req=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * a_host will start by SRP. It needs to set b_hnp_enable before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * actually suspending to start HNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void a_wait_enum(unsigned long foo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) VDBG("a_wait_enum timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!fsl_otg_dev->phy.otg->host->b_hnp_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) fsl_otg_add_timer(&fsl_otg_dev->fsm, a_wait_enum_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) otg_statemachine(&fsl_otg_dev->fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* The timeout callback function to set time out bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void set_tmout(unsigned long indicator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *(int *)indicator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Initialize timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int fsl_otg_init_timers(struct otg_fsm *fsm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* FSM used timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (unsigned long)&fsm->a_wait_vrise_tmout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!a_wait_vrise_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) (unsigned long)&fsm->a_wait_bcon_tmout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!a_wait_bcon_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (unsigned long)&fsm->a_aidl_bdis_tmout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!a_aidl_bdis_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) (unsigned long)&fsm->b_ase0_brst_tmout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!b_ase0_brst_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (unsigned long)&fsm->b_se0_srp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!b_se0_srp_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (unsigned long)&fsm->b_srp_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!b_srp_fail_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) (unsigned long)&fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!a_wait_enum_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* device driver used timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!b_srp_wait_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) TB_DATA_PLS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!b_data_pulse_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) TB_VBUS_PLS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!b_vbus_pulse_tmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Uninitialize timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void fsl_otg_uninit_timers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* FSM used timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) kfree(a_wait_vrise_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) kfree(a_wait_bcon_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) kfree(a_aidl_bdis_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) kfree(b_ase0_brst_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) kfree(b_se0_srp_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) kfree(b_srp_fail_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) kfree(a_wait_enum_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* device driver used timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) kfree(b_srp_wait_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) kfree(b_data_pulse_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) kfree(b_vbus_pulse_tmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct fsl_otg_timer *fsl_otg_get_timer(enum otg_fsm_timer t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct fsl_otg_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* REVISIT: use array of pointers to timers instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) switch (t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case A_WAIT_VRISE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) timer = a_wait_vrise_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) timer = a_wait_vrise_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case A_AIDL_BDIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) timer = a_wait_vrise_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case B_ASE0_BRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) timer = a_wait_vrise_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case B_SE0_SRP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) timer = a_wait_vrise_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case B_SRP_FAIL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) timer = a_wait_vrise_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case A_WAIT_ENUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) timer = a_wait_vrise_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Add timer to timer list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) void fsl_otg_add_timer(struct otg_fsm *fsm, void *gtimer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct fsl_otg_timer *timer = gtimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct fsl_otg_timer *tmp_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Check if the timer is already in the active list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * if so update timer count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) list_for_each_entry(tmp_timer, &active_timers, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (tmp_timer == timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) timer->count = timer->expires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) timer->count = timer->expires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) list_add_tail(&timer->list, &active_timers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void fsl_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct fsl_otg_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) timer = fsl_otg_get_timer(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) fsl_otg_add_timer(fsm, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Remove timer from the timer list; clear timeout status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) void fsl_otg_del_timer(struct otg_fsm *fsm, void *gtimer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct fsl_otg_timer *timer = gtimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct fsl_otg_timer *tmp_timer, *del_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (tmp_timer == timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) list_del(&timer->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void fsl_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct fsl_otg_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) timer = fsl_otg_get_timer(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) fsl_otg_del_timer(fsm, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Reset controller, not reset the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) void otg_reset_controller(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) command = fsl_readl(&usb_dr_regs->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) command |= (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) fsl_writel(command, &usb_dr_regs->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Call suspend/resume routines in host driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int fsl_otg_start_host(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct usb_otg *otg = fsm->otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct fsl_otg *otg_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) container_of(otg->usb_phy, struct fsl_otg, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!otg->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev = otg->host->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Update a_vbus_vld state as a_vbus_vld int is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * in device mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fsm->a_vbus_vld =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* start fsl usb host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (otg_dev->host_working)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) otg_reset_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) VDBG("host on......\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (dev->driver->pm && dev->driver->pm->resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) retval = dev->driver->pm->resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (fsm->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* default-b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) fsl_otg_drv_vbus(fsm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Workaround: b_host can't driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * vbus, but PP in PORTSC needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * be 1 for host to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * So we set drv_vbus bit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * transceiver to 0 thru ULPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) write_ulpi(0x0c, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) otg_dev->host_working = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* stop fsl usb host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!otg_dev->host_working)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) VDBG("host off......\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (dev && dev->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (dev->driver->pm && dev->driver->pm->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) retval = dev->driver->pm->suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (fsm->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* default-b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) fsl_otg_drv_vbus(fsm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) otg_dev->host_working = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Call suspend and resume function in udc driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * to stop and start udc driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct usb_otg *otg = fsm->otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!otg->gadget || !otg->gadget->dev.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) VDBG("gadget %s\n", on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev = otg->gadget->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (dev->driver->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev->driver->resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (dev->driver->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev->driver->suspend(dev, otg_suspend_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Called by initialization code of host driver. Register host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * to the OTG. Suspend host for OTG role detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int fsl_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct fsl_otg *otg_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (otg_dev != fsl_otg_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) otg->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) otg_dev->fsm.a_bus_drop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) otg_dev->fsm.a_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) VDBG("host off......\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) otg->host->otg_port = fsl_otg_initdata.otg_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) otg->host->is_b_host = otg_dev->fsm.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * must leave time for hub_wq to finish its thing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * before yanking the host driver out from under it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * so suspend the host after a short delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) otg_dev->host_working = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) schedule_delayed_work(&otg_dev->otg_event, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* host driver going away */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) OTGSC_STS_USB_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Mini-A cable connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct otg_fsm *fsm = &otg_dev->fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) otg->state = OTG_STATE_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) fsm->protocol = PROTO_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) otg_dev->host_working = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) otg_statemachine(&otg_dev->fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Called by initialization code of udc. Register udc to OTG. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int fsl_otg_set_peripheral(struct usb_otg *otg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct fsl_otg *otg_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) VDBG("otg_dev 0x%x\n", (int)otg_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (otg_dev != fsl_otg_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!gadget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!otg->default_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) otg->gadget->ops->vbus_draw(otg->gadget, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) usb_gadget_vbus_disconnect(otg->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) otg->gadget = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) otg_dev->fsm.b_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) otg_statemachine(&otg_dev->fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) otg->gadget = gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) otg->gadget->is_a_peripheral = !otg_dev->fsm.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) otg_dev->fsm.b_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* start the gadget right away if the ID pin says Mini-B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pr_debug("ID pin=%d\n", otg_dev->fsm.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (otg_dev->fsm.id == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) fsl_otg_start_host(&otg_dev->fsm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) otg_drv_vbus(&otg_dev->fsm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) fsl_otg_start_gadget(&otg_dev->fsm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Delayed pin detect interrupt processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * When the Mini-A cable is disconnected from the board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * the pin-detect interrupt happens before the disconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * interrupts for the connected device(s). In order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * process the disconnect interrupt(s) prior to switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * roles, the pin-detect interrupts are delayed, and handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * by this routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void fsl_otg_event(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct otg_fsm *fsm = &og->fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (fsm->id) { /* switch to gadget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) fsl_otg_start_host(fsm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) otg_drv_vbus(fsm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fsl_otg_start_gadget(fsm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* B-device start SRP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int fsl_otg_start_srp(struct usb_otg *otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct fsl_otg *otg_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (!otg || otg->state != OTG_STATE_B_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (otg_dev != fsl_otg_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) otg_dev->fsm.b_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) otg_statemachine(&otg_dev->fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* A_host suspend will call this function to start hnp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int fsl_otg_start_hnp(struct usb_otg *otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct fsl_otg *otg_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (otg_dev != fsl_otg_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pr_debug("start_hnp...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* clear a_bus_req to enter a_suspend state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) otg_dev->fsm.a_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) otg_statemachine(&otg_dev->fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * Interrupt handler. OTG/host/peripheral share the same int line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * OTG driver clears OTGSC interrupts and leaves USB interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * intact. It needs to have knowledge of some USB interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * such as port change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) irqreturn_t fsl_otg_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 otg_int_src, otg_sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) otg_sc = fsl_readl(&usb_dr_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Only clear otg interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) fsl_writel(otg_sc, &usb_dr_regs->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /*FIXME: ID change not generate when init to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) otg->default_a = (fsm->id == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* process OTG interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (otg_int_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (otg_int_src & OTGSC_INTSTS_USB_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) otg->default_a = (fsm->id == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* clear conn information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (fsm->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) fsm->b_conn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) fsm->a_conn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (otg->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) otg->host->is_b_host = fsm->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (otg->gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) otg->gadget->is_a_peripheral = !fsm->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) VDBG("ID int (ID is %d)\n", fsm->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (fsm->id) { /* switch to gadget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) schedule_delayed_work(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) &((struct fsl_otg *)dev_id)->otg_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) } else { /* switch to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) cancel_delayed_work(&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ((struct fsl_otg *)dev_id)->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) otg_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) fsl_otg_start_gadget(fsm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) otg_drv_vbus(fsm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) fsl_otg_start_host(fsm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static struct otg_fsm_ops fsl_otg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .chrg_vbus = fsl_otg_chrg_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .drv_vbus = fsl_otg_drv_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .loc_conn = fsl_otg_loc_conn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .loc_sof = fsl_otg_loc_sof,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .start_pulse = fsl_otg_start_pulse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .add_timer = fsl_otg_fsm_add_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .del_timer = fsl_otg_fsm_del_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .start_host = fsl_otg_start_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .start_gadget = fsl_otg_start_gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int fsl_otg_conf(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct fsl_otg *fsl_otg_tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (fsl_otg_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* allocate space to fsl otg device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!fsl_otg_tc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) fsl_otg_tc->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!fsl_otg_tc->phy.otg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) kfree(fsl_otg_tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) INIT_LIST_HEAD(&active_timers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) status = fsl_otg_init_timers(&fsl_otg_tc->fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pr_info("Couldn't init OTG timers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mutex_init(&fsl_otg_tc->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Set OTG state machine operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) fsl_otg_tc->fsm.ops = &fsl_otg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* initialize the otg structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) fsl_otg_tc->phy.label = DRIVER_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) fsl_otg_tc->phy.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) fsl_otg_tc->phy.otg->usb_phy = &fsl_otg_tc->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) fsl_otg_tc->phy.otg->set_host = fsl_otg_set_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) fsl_otg_tc->phy.otg->set_peripheral = fsl_otg_set_peripheral;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) fsl_otg_tc->phy.otg->start_hnp = fsl_otg_start_hnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) fsl_otg_tc->phy.otg->start_srp = fsl_otg_start_srp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) fsl_otg_dev = fsl_otg_tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Store the otg transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) status = usb_add_phy(&fsl_otg_tc->phy, USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pr_warn(FSL_OTG_NAME ": unable to register OTG transceiver.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) fsl_otg_uninit_timers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) kfree(fsl_otg_tc->phy.otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) kfree(fsl_otg_tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* OTG Initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int usb_otg_start(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct fsl_otg *p_otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct usb_phy *otg_trans = usb_get_phy(USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct otg_fsm *fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) p_otg = container_of(otg_trans, struct fsl_otg, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) fsm = &p_otg->fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Initialize the state machine structure with default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) fsm->otg = p_otg->phy.otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* We don't require predefined MEM/IRQ resource index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* We don't request_mem_region here to enable resource sharing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * with host/device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pdata->regs = (void *)usb_dr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (pdata->init && pdata->init(pdev) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (pdata->big_endian_mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) _fsl_readl = _fsl_readl_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) _fsl_writel = _fsl_writel_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) _fsl_readl = _fsl_readl_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) _fsl_writel = _fsl_writel_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* request irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) p_otg->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (p_otg->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return p_otg->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) status = request_irq(p_otg->irq, fsl_otg_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) IRQF_SHARED, driver_name, p_otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_dbg(p_otg->phy.dev, "can't get IRQ %d, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) p_otg->irq, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) iounmap(p_otg->dr_mem_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) kfree(p_otg->phy.otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) kfree(p_otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* stop the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) temp &= ~USB_CMD_RUN_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* reset the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) temp |= USB_CMD_CTRL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* wait reset completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* configure the VBUSHS as IDLE(both host and device) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) fsl_writel(temp, &p_otg->dr_mem_map->usbmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* configure PHY interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) temp = fsl_readl(&p_otg->dr_mem_map->portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) switch (pdata->phy_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case FSL_USB2_PHY_ULPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) temp |= PORTSC_PTS_ULPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) case FSL_USB2_PHY_UTMI_WIDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) temp |= PORTSC_PTW_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case FSL_USB2_PHY_UTMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) temp |= PORTSC_PTS_UTMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) fsl_writel(temp, &p_otg->dr_mem_map->portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (pdata->have_sysif_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* configure control enable IO output, big endian register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) temp = __raw_readl(&p_otg->dr_mem_map->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) temp |= USB_CTRL_IOENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) __raw_writel(temp, &p_otg->dr_mem_map->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* disable all interrupt and clear all OTGSC status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * The identification (id) input is FALSE when a Mini-A plug is inserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * Also: record initial state of ID pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) p_otg->phy.otg->state = OTG_STATE_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) p_otg->fsm.id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) p_otg->phy.otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) p_otg->fsm.id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) pr_debug("initial ID pin=%d\n", p_otg->fsm.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* enable OTG ID pin interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) temp |= OTGSC_INTR_USB_ID_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int fsl_otg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (!dev_get_platdata(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* configure the OTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = fsl_otg_conf(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_err(&pdev->dev, "Couldn't configure OTG module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* start OTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret = usb_otg_start(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dev_err(&pdev->dev, "Can't init FSL OTG device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int fsl_otg_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) usb_remove_phy(&fsl_otg_dev->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) free_irq(fsl_otg_dev->irq, fsl_otg_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) iounmap((void *)usb_dr_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) fsl_otg_uninit_timers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) kfree(fsl_otg_dev->phy.otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) kfree(fsl_otg_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (pdata->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pdata->exit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct platform_driver fsl_otg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .probe = fsl_otg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .remove = fsl_otg_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .name = driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) module_platform_driver(fsl_otg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) MODULE_DESCRIPTION(DRIVER_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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