Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * drivers/usb/musb/ux500_dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * U8500 DMA support code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2009 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2011 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *	Praveena Nadahally <praveen.nadahally@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *	Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/pfn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/platform_data/usb-musb-ux500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 					"iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 					"oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct ux500_dma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct dma_channel channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct ux500_dma_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct musb_hw_ep *hw_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned int cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u8 ch_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u8 is_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8 is_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct ux500_dma_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct dma_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	dma_addr_t phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Work function invoked from DMA callback to handle rx transfers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void ux500_dma_callback(void *private_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct dma_channel *channel = private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct ux500_dma_channel *ux500_channel = channel->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct musb *musb = hw_ep->musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		hw_ep->epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ux500_channel->channel.actual_len = ux500_channel->cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static bool ux500_configure_channel(struct dma_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 				u16 packet_sz, u8 mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				dma_addr_t dma_addr, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct ux500_dma_channel *ux500_channel = channel->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct dma_chan *dma_chan = ux500_channel->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct dma_async_tx_descriptor *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct scatterlist sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct dma_slave_config slave_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	enum dma_slave_buswidth addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct musb *musb = ux500_channel->controller->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 					ux500_channel->controller->phy_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	dev_dbg(musb->controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		"packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		packet_sz, mode, (unsigned long long) dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		len, ux500_channel->is_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ux500_channel->cur_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	sg_init_table(&sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 					    offset_in_page(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	sg_dma_address(&sg) = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	sg_dma_len(&sg) = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	slave_conf.direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	slave_conf.src_addr = usb_fifo_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	slave_conf.src_addr_width = addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	slave_conf.src_maxburst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	slave_conf.dst_addr = usb_fifo_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	slave_conf.dst_addr_width = addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	slave_conf.dst_maxburst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	slave_conf.device_fc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	dmaengine_slave_config(dma_chan, &slave_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 					     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (!dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	dma_desc->callback = ux500_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	dma_desc->callback_param = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	dma_async_issue_pending(dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				struct musb_hw_ep *hw_ep, u8 is_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct ux500_dma_controller *controller = container_of(c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			struct ux500_dma_controller, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct ux500_dma_channel *ux500_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct musb *musb = controller->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u8 ch_num = hw_ep->epnum - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * to specified hw_ep. For example DMA channel 0 can only be allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * to hw_ep 1 and 9.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (ch_num > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		ch_num -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				&(controller->rx_channel[ch_num]) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* Check if channel is already used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (ux500_channel->is_allocated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ux500_channel->hw_ep = hw_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ux500_channel->is_allocated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		hw_ep->epnum, is_tx, ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return &(ux500_channel->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void ux500_dma_channel_release(struct dma_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct ux500_dma_channel *ux500_channel = channel->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct musb *musb = ux500_channel->controller->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (ux500_channel->is_allocated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		ux500_channel->is_allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		channel->status = MUSB_DMA_STATUS_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		channel->actual_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int ux500_dma_is_compatible(struct dma_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		u16 maxpacket, void *buf, u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if ((maxpacket & 0x3)		||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		((unsigned long int) buf & 0x3)	||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		(length < 512)		||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		(length & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int ux500_dma_channel_program(struct dma_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				u16 packet_sz, u8 mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				dma_addr_t dma_addr, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		channel->status == MUSB_DMA_STATUS_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	channel->status = MUSB_DMA_STATUS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	channel->actual_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		channel->status = MUSB_DMA_STATUS_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int ux500_dma_channel_abort(struct dma_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct ux500_dma_channel *ux500_channel = channel->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct ux500_dma_controller *controller = ux500_channel->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct musb *musb = controller->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u16 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		ux500_channel->ch_num, ux500_channel->is_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (channel->status == MUSB_DMA_STATUS_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		if (ux500_channel->is_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			csr = musb_readw(epio, MUSB_TXCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			csr &= ~(MUSB_TXCSR_AUTOSET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				 MUSB_TXCSR_DMAENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				 MUSB_TXCSR_DMAMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			musb_writew(epio, MUSB_TXCSR, csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			csr = musb_readw(epio, MUSB_RXCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				 MUSB_RXCSR_DMAENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				 MUSB_RXCSR_DMAMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			musb_writew(epio, MUSB_RXCSR, csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		dmaengine_terminate_all(ux500_channel->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		channel->status = MUSB_DMA_STATUS_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void ux500_dma_controller_stop(struct ux500_dma_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct ux500_dma_channel *ux500_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct dma_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	u8 ch_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		channel = &controller->rx_channel[ch_num].channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		ux500_channel = channel->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		ux500_dma_channel_release(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (ux500_channel->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			dma_release_channel(ux500_channel->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		channel = &controller->tx_channel[ch_num].channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		ux500_channel = channel->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		ux500_dma_channel_release(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		if (ux500_channel->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			dma_release_channel(ux500_channel->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct ux500_dma_channel *ux500_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct musb *musb = controller->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct ux500_musb_board_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct dma_channel *dma_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	char **chan_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	u32 ch_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	u8 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	u8 is_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	void **param_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct ux500_dma_channel *channel_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!plat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		dev_err(musb->controller, "No platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	data = plat->board_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Prepare the loop for RX channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	channel_array = controller->rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	param_array = data ? data->dma_rx_param_array : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	chan_names = (char **)iep_chan_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	for (dir = 0; dir < 2; dir++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		for (ch_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		     ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		     ch_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			ux500_channel = &channel_array[ch_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			ux500_channel->controller = controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			ux500_channel->ch_num = ch_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			ux500_channel->is_tx = is_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			dma_channel = &(ux500_channel->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			dma_channel->private_data = ux500_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			dma_channel->status = MUSB_DMA_STATUS_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			dma_channel->max_len = SZ_16M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			ux500_channel->dma_chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				dma_request_chan(dev, chan_names[ch_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			if (IS_ERR(ux500_channel->dma_chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				ux500_channel->dma_chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 					dma_request_channel(mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 							    data ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 							    data->dma_filter :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 							    NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 							    param_array ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 							    param_array[ch_num] :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 							    NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			if (!ux500_channel->dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				ERR("Dma pipe allocation error dir=%d ch=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					dir, ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				/* Release already allocated channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				ux500_dma_controller_stop(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 				return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		/* Prepare the loop for TX channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		channel_array = controller->tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		param_array = data ? data->dma_tx_param_array : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		chan_names = (char **)oep_chan_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		is_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void ux500_dma_controller_destroy(struct dma_controller *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct ux500_dma_controller *controller = container_of(c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			struct ux500_dma_controller, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ux500_dma_controller_stop(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	kfree(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ux500_dma_controller_create(struct musb *musb, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	struct ux500_dma_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	struct platform_device *pdev = to_platform_device(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	struct resource	*iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (!controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		goto kzalloc_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	controller->private_data = musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	/* Save physical address for DMA controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (!iomem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		dev_err(musb->controller, "no memory resource defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		goto plat_get_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	controller->phy_base = (dma_addr_t) iomem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	controller->controller.channel_alloc = ux500_dma_channel_allocate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	controller->controller.channel_release = ux500_dma_channel_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	controller->controller.channel_program = ux500_dma_channel_program;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	controller->controller.channel_abort = ux500_dma_channel_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	controller->controller.is_compatible = ux500_dma_is_compatible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	ret = ux500_dma_controller_start(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		goto plat_get_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return &controller->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) plat_get_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	kfree(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) kzalloc_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) EXPORT_SYMBOL_GPL(ux500_dma_controller_create);