Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2006 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef __TUSB6010_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define __TUSB6010_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* VLYNQ control register. 32-bit at offset 0x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define TUSB_VLYNQ_CTRL			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TUSB_BASE_OFFSET		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* FIFO registers 32-bit at offset 0x600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TUSB_FIFO_BASE			0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Device System & Control registers. 32-bit at offset 0x800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TUSB_SYS_REG_BASE		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TUSB_DEV_CONF			(TUSB_SYS_REG_BASE + 0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define		TUSB_DEV_CONF_USB_HOST_MODE		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define		TUSB_DEV_CONF_PROD_TEST_MODE		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define		TUSB_DEV_CONF_SOFT_ID			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define		TUSB_DEV_CONF_ID_SEL			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TUSB_PHY_OTG_CTRL_ENABLE	(TUSB_SYS_REG_BASE + 0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TUSB_PHY_OTG_CTRL		(TUSB_SYS_REG_BASE + 0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define		TUSB_PHY_OTG_CTRL_WRPROTECT		(0xa5 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define		TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP		(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define		TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN	(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define		TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN	(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define		TUSB_PHY_OTG_CTRL_TESTM2		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define		TUSB_PHY_OTG_CTRL_TESTM1		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define		TUSB_PHY_OTG_CTRL_TESTM0		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define		TUSB_PHY_OTG_CTRL_TX_DATA2		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define		TUSB_PHY_OTG_CTRL_TX_GZ2		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define		TUSB_PHY_OTG_CTRL_TX_ENABLE2		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define		TUSB_PHY_OTG_CTRL_DM_PULLDOWN		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define		TUSB_PHY_OTG_CTRL_DP_PULLDOWN		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define		TUSB_PHY_OTG_CTRL_OSC_EN		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define		TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v)	(((v) & 3) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define		TUSB_PHY_OTG_CTRL_PD			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define		TUSB_PHY_OTG_CTRL_PLL_ON		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define		TUSB_PHY_OTG_CTRL_EXT_RPU		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define		TUSB_PHY_OTG_CTRL_PWR_GOOD		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define		TUSB_PHY_OTG_CTRL_RESET			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define		TUSB_PHY_OTG_CTRL_SUSPENDM		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define		TUSB_PHY_OTG_CTRL_CLK_MODE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /*OTG status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TUSB_DEV_OTG_STAT		(TUSB_SYS_REG_BASE + 0x00c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define		TUSB_DEV_OTG_STAT_PWR_CLK_GOOD		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define		TUSB_DEV_OTG_STAT_SESS_END		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define		TUSB_DEV_OTG_STAT_SESS_VALID		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define		TUSB_DEV_OTG_STAT_VBUS_VALID		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define		TUSB_DEV_OTG_STAT_VBUS_SENSE		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define		TUSB_DEV_OTG_STAT_ID_STATUS		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define		TUSB_DEV_OTG_STAT_HOST_DISCON		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define		TUSB_DEV_OTG_STAT_LINE_STATE		(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define		TUSB_DEV_OTG_STAT_DP_ENABLE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define		TUSB_DEV_OTG_STAT_DM_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TUSB_DEV_OTG_TIMER		(TUSB_SYS_REG_BASE + 0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #	define TUSB_DEV_OTG_TIMER_ENABLE		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #	define TUSB_DEV_OTG_TIMER_VAL(v)		((v) & 0x07ffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TUSB_PRCM_REV			(TUSB_SYS_REG_BASE + 0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* PRCM configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TUSB_PRCM_CONF			(TUSB_SYS_REG_BASE + 0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define		TUSB_PRCM_CONF_SFW_CPEN		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define		TUSB_PRCM_CONF_SYS_CLKSEL(v)	(((v) & 3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* PRCM management register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TUSB_PRCM_MNGMT			(TUSB_SYS_REG_BASE + 0x01c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define		TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v)	(((v) & 0xf) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define		TUSB_PRCM_MNGMT_SRP_FIX_EN		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define		TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v)	(((v) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define		TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN	(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define		TUSB_PRCM_MNGMT_DFT_CLK_DIS		(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define		TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define		TUSB_PRCM_MNGMT_OTG_SESS_END_EN		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define		TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define		TUSB_PRCM_MNGMT_OTG_ID_PULLUP		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define		TUSB_PRCM_MNGMT_15_SW_EN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define		TUSB_PRCM_MNGMT_33_SW_EN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define		TUSB_PRCM_MNGMT_5V_CPEN			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define		TUSB_PRCM_MNGMT_PM_IDLE			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define		TUSB_PRCM_MNGMT_DEV_IDLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* Wake-up source clear and mask registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TUSB_PRCM_WAKEUP_SOURCE		(TUSB_SYS_REG_BASE + 0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TUSB_PRCM_WAKEUP_CLEAR		(TUSB_SYS_REG_BASE + 0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TUSB_PRCM_WAKEUP_MASK		(TUSB_SYS_REG_BASE + 0x02c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define		TUSB_PRCM_WAKEUP_RESERVED_BITS	(0xffffe << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define		TUSB_PRCM_WGPIO_7	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define		TUSB_PRCM_WGPIO_6	(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define		TUSB_PRCM_WGPIO_5	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define		TUSB_PRCM_WGPIO_4	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define		TUSB_PRCM_WGPIO_3	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define		TUSB_PRCM_WGPIO_2	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define		TUSB_PRCM_WGPIO_1	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define		TUSB_PRCM_WGPIO_0	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define		TUSB_PRCM_WHOSTDISCON	(1 << 4)	/* Host disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define		TUSB_PRCM_WBUS		(1 << 3)	/* USB bus resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define		TUSB_PRCM_WNORCS	(1 << 2)	/* NOR chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define		TUSB_PRCM_WVBUS		(1 << 1)	/* OTG PHY VBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define		TUSB_PRCM_WID		(1 << 0)	/* OTG PHY ID detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TUSB_PULLUP_1_CTRL		(TUSB_SYS_REG_BASE + 0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TUSB_PULLUP_2_CTRL		(TUSB_SYS_REG_BASE + 0x034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TUSB_INT_CTRL_REV		(TUSB_SYS_REG_BASE + 0x038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TUSB_INT_CTRL_CONF		(TUSB_SYS_REG_BASE + 0x03c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TUSB_USBIP_INT_SRC		(TUSB_SYS_REG_BASE + 0x040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TUSB_USBIP_INT_SET		(TUSB_SYS_REG_BASE + 0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TUSB_USBIP_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TUSB_USBIP_INT_MASK		(TUSB_SYS_REG_BASE + 0x04c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TUSB_DMA_INT_SRC		(TUSB_SYS_REG_BASE + 0x050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TUSB_DMA_INT_SET		(TUSB_SYS_REG_BASE + 0x054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TUSB_DMA_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TUSB_DMA_INT_MASK		(TUSB_SYS_REG_BASE + 0x05c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TUSB_GPIO_INT_SRC		(TUSB_SYS_REG_BASE + 0x060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TUSB_GPIO_INT_SET		(TUSB_SYS_REG_BASE + 0x064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TUSB_GPIO_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TUSB_GPIO_INT_MASK		(TUSB_SYS_REG_BASE + 0x06c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* NOR flash interrupt source registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TUSB_INT_SRC			(TUSB_SYS_REG_BASE + 0x070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TUSB_INT_SRC_SET		(TUSB_SYS_REG_BASE + 0x074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TUSB_INT_SRC_CLEAR		(TUSB_SYS_REG_BASE + 0x078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TUSB_INT_MASK			(TUSB_SYS_REG_BASE + 0x07c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define		TUSB_INT_SRC_TXRX_DMA_DONE		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define		TUSB_INT_SRC_USB_IP_CORE		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define		TUSB_INT_SRC_OTG_TIMEOUT		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define		TUSB_INT_SRC_VBUS_SENSE_CHNG		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define		TUSB_INT_SRC_ID_STATUS_CHNG		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define		TUSB_INT_SRC_DEV_WAKEUP			(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define		TUSB_INT_SRC_DEV_READY			(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define		TUSB_INT_SRC_USB_IP_TX			(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define		TUSB_INT_SRC_USB_IP_RX			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define		TUSB_INT_SRC_USB_IP_VBUS_ERR		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define		TUSB_INT_SRC_USB_IP_VBUS_REQ		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define		TUSB_INT_SRC_USB_IP_DISCON		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define		TUSB_INT_SRC_USB_IP_CONN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define		TUSB_INT_SRC_USB_IP_SOF			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define		TUSB_INT_SRC_USB_IP_RST_BABBLE		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define		TUSB_INT_SRC_USB_IP_RESUME		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define		TUSB_INT_SRC_USB_IP_SUSPEND		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* NOR flash interrupt registers reserved bits. Must be written as 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define		TUSB_INT_MASK_RESERVED_17		(0x3fff << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define		TUSB_INT_MASK_RESERVED_13		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define		TUSB_INT_MASK_RESERVED_8		(0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define		TUSB_INT_SRC_RESERVED_26		(0x1f << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define		TUSB_INT_SRC_RESERVED_18		(0x3f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define		TUSB_INT_SRC_RESERVED_10		(0x03 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Reserved bits for NOR flash interrupt mask and clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define		TUSB_INT_MASK_RESERVED_BITS	(TUSB_INT_MASK_RESERVED_17 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 						TUSB_INT_MASK_RESERVED_13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 						TUSB_INT_MASK_RESERVED_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Reserved bits for NOR flash interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define		TUSB_INT_SRC_RESERVED_BITS	(TUSB_INT_SRC_RESERVED_26 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 						TUSB_INT_SRC_RESERVED_18 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 						TUSB_INT_SRC_RESERVED_10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TUSB_GPIO_REV			(TUSB_SYS_REG_BASE + 0x080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TUSB_GPIO_CONF			(TUSB_SYS_REG_BASE + 0x084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TUSB_DMA_CTRL_REV		(TUSB_SYS_REG_BASE + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TUSB_DMA_REQ_CONF		(TUSB_SYS_REG_BASE + 0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TUSB_EP0_CONF			(TUSB_SYS_REG_BASE + 0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TUSB_DMA_EP_MAP			(TUSB_SYS_REG_BASE + 0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Offsets from each ep base register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TUSB_EP_TX_OFFSET		0x10c	/* EP_IN in docs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TUSB_EP_RX_OFFSET		0x14c	/* EP_OUT in docs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TUSB_EP_MAX_PACKET_SIZE_OFFSET	0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TUSB_WAIT_COUNT			(TUSB_SYS_REG_BASE + 0x1c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TUSB_SCRATCH_PAD		(TUSB_SYS_REG_BASE + 0x1c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TUSB_PROD_TEST_RESET		(TUSB_SYS_REG_BASE + 0x1d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Device System & Control register bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TUSB_INT_CTRL_CONF_INT_RELCYC(v)	(((v) & 0x7) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TUSB_INT_CTRL_CONF_INT_POLARITY		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TUSB_INT_CTRL_CONF_INT_MODE		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TUSB_GPIO_CONF_DMAREQ(v)		(((v) & 0x3f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TUSB_DMA_REQ_CONF_BURST_SIZE(v)		(((v) & 3) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v)		(((v) & 0x3f) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v)	(((v) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TUSB_EP0_CONFIG_SW_EN			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TUSB_EP0_CONFIG_DIR_TX			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TUSB_EP0_CONFIG_XFR_SIZE(v)		((v) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TUSB_EP_CONFIG_SW_EN			(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TUSB_EP_CONFIG_XFR_SIZE(v)		((v) & 0x7fffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TUSB_PROD_TEST_RESET_VAL		0xa596
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TUSB_EP_FIFO(ep)			(TUSB_FIFO_BASE + (ep) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TUSB_DIDR1_LO				(TUSB_SYS_REG_BASE + 0x1f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TUSB_DIDR1_HI				(TUSB_SYS_REG_BASE + 0x1fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define		TUSB_DIDR1_HI_CHIP_REV(v)		(((v) >> 17) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define			TUSB_DIDR1_HI_REV_20		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define			TUSB_DIDR1_HI_REV_30		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define			TUSB_DIDR1_HI_REV_31		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TUSB_REV_10	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TUSB_REV_20	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TUSB_REV_30	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TUSB_REV_31	0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif /* __TUSB6010_H__ */