^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TUSB6010 USB 2.0 OTG Dual Role controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - Driver assumes that interface to external host (main CPU) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * configured for NOR FLASH interface instead of VLYNQ serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/prefetch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb/usb_phy_generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct tusb6010_glue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct platform_device *musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct platform_device *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void tusb_musb_set_vbus(struct musb *musb, int is_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Checks the revision. We need to use the DMA register as 3.0 does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static u8 tusb_get_revision(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 die_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (TUSB_REV_MAJOR(rev) == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) TUSB_DIDR1_HI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (die_id >= TUSB_DIDR1_HI_REV_31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) rev |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void tusb_print_revision(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) rev = musb->tusb_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "prcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "dieid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "rev",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) | TUSB_PHY_OTG_CTRL_TESTM0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Disables power detection in PHY for the duration of idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void tusb_wbus_quirk(struct musb *musb, int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static u32 phy_otg_ctrl, phy_otg_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) | phy_otg_ena | WBUS_QUIRK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) musb_readl(tbase, TUSB_PHY_OTG_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) & TUSB_PHY_OTG_CTRL_TESTM2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) musb_readl(tbase, TUSB_PHY_OTG_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) phy_otg_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) phy_otg_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static u32 tusb_fifo_offset(u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0x200 + (epnum * 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static u32 tusb_ep_offset(u8 epnum, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0x10 + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* TUSB mapping: "flat" plus ep0 special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void tusb_ep_select(void __iomem *mbase, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) musb_writeb(mbase, MUSB_INDEX, epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u8 tusb_readb(void __iomem *addr, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tmp = __raw_readw(addr + (offset & ~1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (offset & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val = (tmp >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) val = tmp & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void tusb_writeb(void __iomem *addr, u32 offset, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tmp = __raw_readw(addr + (offset & ~1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (offset & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tmp = (data << 8) | (tmp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tmp = (tmp & 0xff00) | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __raw_writew(tmp, addr + (offset & ~1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * TUSB 6010 may use a parallel bus that doesn't support byte ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * so both loading and unloading FIFOs need explicit byte counts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (len > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) for (i = 0; i < (len >> 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) memcpy(&val, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) musb_writel(fifo, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) len %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Write the rest 1 - 3 bytes to FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) memcpy(&val, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) musb_writel(fifo, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (len > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < (len >> 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val = musb_readl(fifo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) memcpy(buf, &val, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) len %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Read the rest 1 - 3 bytes from FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = musb_readl(fifo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) memcpy(buf, &val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct musb *musb = hw_ep->musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void __iomem *ep_conf = hw_ep->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void __iomem *fifo = hw_ep->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 epnum = hw_ep->epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) prefetch(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 'T', epnum, fifo, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) TUSB_EP_CONFIG_XFR_SIZE(len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) TUSB_EP0_CONFIG_XFR_SIZE(len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (likely((0x01 & (unsigned long) buf) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Best case is 32bit-aligned destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if ((0x02 & (unsigned long) buf) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) iowrite32_rep(fifo, buf, len >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) buf += (len & ~0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Cannot use writesw, fifo is 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) for (i = 0; i < (len >> 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val = (u32)(*(u16 *)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) buf += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) val |= (*(u16 *)buf) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) buf += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) musb_writel(fifo, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) tusb_fifo_write_unaligned(fifo, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct musb *musb = hw_ep->musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem *ep_conf = hw_ep->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void __iomem *fifo = hw_ep->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 epnum = hw_ep->epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 'R', epnum, fifo, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) TUSB_EP_CONFIG_XFR_SIZE(len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (likely((0x01 & (unsigned long) buf) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Best case is 32bit-aligned destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((0x02 & (unsigned long) buf) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ioread32_rep(fifo, buf, len >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) buf += (len & ~0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Cannot use readsw, fifo is 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (i = 0; i < (len >> 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) val = musb_readl(fifo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) *(u16 *)buf = (u16)(val & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) buf += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *(u16 *)buf = (u16)(val >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) buf += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tusb_fifo_read_unaligned(fifo, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct musb *the_musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* This is used by gadget drivers, and OTG transceiver logic, allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * at most mA current to be drawn from VBUS during a Default-B session
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * mode), or low power Default-B sessions, something else supplies power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Caller must take care of locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int tusb_draw_power(struct usb_phy *x, unsigned mA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct musb *musb = the_musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* tps65030 seems to consume max 100mA, with maybe 60mA available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * (measured on one board) for things other than tps and tusb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Boards sharing the CPU clock with CLKIN will need to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * certain idle sleep states while the USB link is active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * The actual current usage would be very board-specific. For now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * it's simpler to just use an aggregate (also board-specific).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (x->otg->default_a || mA < (musb->min_power << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mA = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (mA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) musb->is_bus_powered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) musb->is_bus_powered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* workaround for issue 13: change clock during chip idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * (to be fixed in rev3 silicon) ... symptoms include disconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * or looping suspend/resume cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void tusb_set_clock_source(struct musb *musb, unsigned mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) reg = musb_readl(tbase, TUSB_PRCM_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* 0 = refclk (clkin, XI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * 1 = PHY 60 MHz (internal PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * 2 = not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * 3 = what?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (mode > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) musb_writel(tbase, TUSB_PRCM_CONF, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* FIXME tusb6010_platform_retime(mode == 0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Idle TUSB6010 until next wake-up event; NOR access always wakes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Other code ensures that we idle unless we're connected _and_ the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * USB link is not suspended ... and tells us the relevant wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * events. SW_EN for voltage is handled separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if ((wakeup_enables & TUSB_PRCM_WBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) && (musb->tusb_revision == TUSB_REV_30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tusb_wbus_quirk(musb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tusb_set_clock_source(musb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) wakeup_enables |= TUSB_PRCM_WNORCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* REVISIT writeup of WID implies that if WID set and ID is grounded,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Presumably that's mostly to save power, hence WID is immaterial ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (is_host_active(musb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * Updates cable VBUS status. Caller must take care of locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int tusb_musb_vbus_status(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 otg_stat, prcm_mngmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Temporarily enable VBUS detection if it was disabled for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * suspend mode. Unless it's enabled otg_stat and devctl will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * not show correct VBUS state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 tmp = prcm_mngmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void musb_do_idle(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct musb *musb = from_timer(musb, t, dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if ((musb->a_wait_bcon != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) && (musb->idle_timeout == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) || time_after(jiffies, musb->idle_timeout))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) usb_otg_state_string(musb->xceiv->otg->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case OTG_STATE_A_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) tusb_musb_set_vbus(musb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!musb->is_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 wakeups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* wait until hub_wq handles port change status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (is_host_active(musb) && (musb->port1_status >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!musb->gadget_driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) wakeups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) wakeups = TUSB_PRCM_WHOSTDISCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) | TUSB_PRCM_WBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) | TUSB_PRCM_WVBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) wakeups |= TUSB_PRCM_WID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) tusb_allow_idle(musb, wakeups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Maybe put TUSB6010 into idle mode mode depending on USB link status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * like "disconnected" or "suspended". We'll be woken out of it by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * connect, resume, or disconnect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Needs to be called as the last function everywhere where there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * register access to TUSB6010 because of NOR flash wake-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Caller should own controller spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Delay because peripheral enables D+ pullup 3msec after SE0, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * we don't want to treat that full speed J as a wakeup event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * ... peripherals must draw only suspend current after 10 msec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static unsigned long last_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) timeout = default_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Never idle if active, or when VBUS timeout is not set as host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (musb->is_active || ((musb->a_wait_bcon == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_dbg(musb->controller, "%s active, deleting timer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) usb_otg_state_string(musb->xceiv->otg->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) del_timer(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) last_timer = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (time_after(last_timer, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!timer_pending(&musb->dev_timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) last_timer = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) last_timer = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) usb_otg_state_string(musb->xceiv->otg->state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) (unsigned long)jiffies_to_msecs(timeout - jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mod_timer(&musb->dev_timer, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* ticks of 60 MHz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define DEVCLOCK 60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define OTG_TIMER_MS(msecs) ((msecs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) | TUSB_DEV_OTG_TIMER_ENABLE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static void tusb_musb_set_vbus(struct musb *musb, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 conf, prcm, timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u8 devctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct usb_otg *otg = musb->xceiv->otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* HDRC controls CPEN, but beware current surges during device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * connect. They can trigger transient overcurrent conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * that must be ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) conf = musb_readl(tbase, TUSB_DEV_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) otg->default_a = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) devctl |= MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) conf |= TUSB_DEV_CONF_USB_HOST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 otg_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* If ID pin is grounded, we want to be a_idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case OTG_STATE_A_WAIT_VRISE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case OTG_STATE_A_WAIT_VFALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) musb->xceiv->otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) musb->xceiv->otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) musb->is_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) otg->default_a = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) musb->is_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) otg->default_a = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MUSB_DEV_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) devctl &= ~MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) musb_writel(tbase, TUSB_DEV_CONF, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) usb_otg_state_string(musb->xceiv->otg->state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) musb_readb(musb->mregs, MUSB_DEVCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) musb_readl(tbase, TUSB_DEV_OTG_STAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) conf, prcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Sets the mode to OTG, peripheral or host by changing the ID detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Caller must take care of locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Note that if a mini-A cable is plugged in the ID line will stay down as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * the weak ID pull-up is not able to pull the ID up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) switch (musb_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case MUSB_HOST: /* Disable PHY ID detect, ground ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_conf |= TUSB_DEV_CONF_ID_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case MUSB_OTG: /* Use PHY ID detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) musb_writel(tbase, TUSB_PHY_OTG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if ((musb_mode == MUSB_PERIPHERAL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) INFO("Cannot be peripheral with mini-A cable "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "otg_stat: %08x\n", otg_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned long idle_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct usb_otg *otg = musb->xceiv->otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* ID pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int default_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) otg->default_a = default_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) tusb_musb_set_vbus(musb, default_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Don't allow idling immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (default_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) idle_timeout = jiffies + (HZ * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* VBUS state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* B-dev state machine: no vbus ~= disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!otg->default_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* ? musb_root_disconnect(musb); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) musb->port1_status &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ~(USB_PORT_STAT_CONNECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) | USB_PORT_STAT_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) | USB_PORT_STAT_LOW_SPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) | USB_PORT_STAT_HIGH_SPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) | USB_PORT_STAT_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* INTR_DISCONNECT can hide... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) musb->int_usb |= MUSB_INTR_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) musb->is_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) idle_timeout = jiffies + (1 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) schedule_delayed_work(&musb->irq_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) } else /* A-dev state machine */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) case OTG_STATE_A_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) musb_platform_set_vbus(musb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* CONNECT can wake if a_wait_bcon is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (musb->a_wait_bcon != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) musb->is_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) musb->is_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * OPT FS A TD.4.6 needs few seconds for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * A_WAIT_VRISE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) idle_timeout = jiffies + (2 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case OTG_STATE_A_WAIT_VRISE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* ignore; A-session-valid < VBUS_VALID/2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * we monitor this with the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case OTG_STATE_A_WAIT_VFALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* REVISIT this irq triggers during short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * spikes caused by enumeration ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (musb->vbuserr_retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) musb->vbuserr_retry--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) tusb_musb_set_vbus(musb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) musb->vbuserr_retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) = VBUSERR_RETRY_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) tusb_musb_set_vbus(musb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* OTG timer expiration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u8 devctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_dbg(musb->controller, "%s timer, %03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case OTG_STATE_A_WAIT_VRISE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* VBUS has probably been valid for a while now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * but may well have bounced out of range a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if ((devctl & MUSB_DEVCTL_VBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) != MUSB_DEVCTL_VBUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_dbg(musb->controller, "devctl %02x\n", devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) musb->is_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) idle_timeout = jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) + msecs_to_jiffies(musb->a_wait_bcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* REVISIT report overcurrent to hub? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ERR("vbus too slow, devctl %02x\n", devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) tusb_musb_set_vbus(musb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (musb->a_wait_bcon != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) idle_timeout = jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) + msecs_to_jiffies(musb->a_wait_bcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case OTG_STATE_A_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case OTG_STATE_B_WAIT_ACON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) schedule_delayed_work(&musb->irq_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return idle_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct musb *musb = __hci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned long flags, idle_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u32 int_mask, int_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Mask all interrupts to allow using both edge and level GPIO irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int_mask = musb_readl(tbase, TUSB_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) musb->int_usb = (u8) int_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Acknowledge wake-up source interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (musb->tusb_revision == TUSB_REV_30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) tusb_wbus_quirk(musb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* there are issues re-locking the PLL on wakeup ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* work around issue 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) musb_writel(tbase, TUSB_SCRATCH_PAD, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (reg == i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev_dbg(musb->controller, "TUSB NOR not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* work around issue 13 (2nd half) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) tusb_set_clock_source(musb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (reg & ~TUSB_PRCM_WNORCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) musb->is_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) schedule_delayed_work(&musb->irq_work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_dbg(musb->controller, "wake %sactive %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) musb->is_active ? "" : "in", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (int_src & TUSB_INT_SRC_USB_IP_CONN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) del_timer(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* OTG state change reports (annoyingly) not issued by Mentor core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) | TUSB_INT_SRC_OTG_TIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) | TUSB_INT_SRC_ID_STATUS_CHNG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) idle_timeout = tusb_otg_ints(musb, int_src, tbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * Just clear the DMA interrupt if it comes as the completion for both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * TX and RX is handled by the DMA callback in tusb6010_omap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) musb->int_tx = (musb_src & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) musb->int_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) musb->int_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) musb_interrupt(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) musb_writel(tbase, TUSB_INT_SRC_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) int_src & ~TUSB_INT_MASK_RESERVED_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) tusb_musb_try_idle(musb, idle_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) musb_writel(tbase, TUSB_INT_MASK, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int dma_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * Enables TUSB6010. Caller must take care of locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * REVISIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * - Check what is unnecessary in MGC_HdrcStart()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static void tusb_musb_enable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Clear all subsystem interrups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Acknowledge pending interrupt(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Only 0 clock cycles for minimum interrupt de-assertion time and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * interrupt polarity active low seems to work reliably here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) musb_writel(tbase, TUSB_INT_CTRL_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) TUSB_INT_CTRL_CONF_INT_RELCYC(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* maybe force into the Default-A OTG state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) & TUSB_DEV_OTG_STAT_ID_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) musb_writel(tbase, TUSB_INT_SRC_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) TUSB_INT_SRC_ID_STATUS_CHNG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (is_dma_capable() && dma_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) printk(KERN_WARNING "%s %s: dma not reactivated\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) __FILE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dma_off = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * Disables TUSB6010. Caller must take care of locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static void tusb_musb_disable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* FIXME stop DMA, IRQs, timers, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) del_timer(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (is_dma_capable() && !dma_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) printk(KERN_WARNING "%s %s: dma still active\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) __FILE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dma_off = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * Sets up TUSB6010 CPU interface specific signals and registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * Note: Settings optimized for OMAP24xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static void tusb_setup_cpu_interface(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * Disable GPIO[5:0] pullups (used as output DMA requests)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Don't disable GPIO[7:6] as they are needed for wake-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * de-assertion time 2 system clocks p 62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) musb_writel(tbase, TUSB_DMA_REQ_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* Set 0 wait count for synchronous burst access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) musb_writel(tbase, TUSB_WAIT_COUNT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static int tusb_musb_start(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) void __iomem *tbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (musb->board_set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret = musb->board_set_power(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) TUSB_PROD_TEST_RESET_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) musb->tusb_revision = tusb_get_revision(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) tusb_print_revision(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (musb->tusb_revision < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) musb->tusb_revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * NOR FLASH interface is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Select PHY free running 60MHz as a system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) tusb_set_clock_source(musb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * power saving, enable VBus detect and session end comparators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * enable IDpullup, enable VBus charging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) musb_writel(tbase, TUSB_PRCM_MNGMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) tusb_setup_cpu_interface(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* simplify: always sense/pullup ID pins, as if in OTG mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (musb->board_set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) musb->board_set_power(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int tusb_musb_init(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) void __iomem *sync = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (IS_ERR_OR_NULL(musb->xceiv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pdev = to_platform_device(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* dma address for async dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) pr_debug("no async dma resource?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) musb->async = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* dma address for sync dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pr_debug("no sync dma resource?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) musb->sync = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) sync = ioremap(mem->start, resource_size(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (!sync) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) pr_debug("ioremap for sync failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) musb->sync_va = sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * FIFOs at 0x600, TUSB at 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) musb->mregs += TUSB_BASE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ret = tusb_musb_start(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) printk(KERN_ERR "Could not start tusb6010 (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) musb->isr = tusb_musb_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) musb->xceiv->set_power = tusb_draw_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) the_musb = musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) timer_setup(&musb->dev_timer, musb_do_idle, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) iounmap(sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) usb_put_phy(musb->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int tusb_musb_exit(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) del_timer_sync(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) the_musb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (musb->board_set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) musb->board_set_power(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) iounmap(musb->sync_va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) usb_put_phy(musb->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static const struct musb_platform_ops tusb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) MUSB_G_NO_SKB_RESERVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .init = tusb_musb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .exit = tusb_musb_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .ep_offset = tusb_ep_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .ep_select = tusb_ep_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .fifo_offset = tusb_fifo_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .readb = tusb_readb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .writeb = tusb_writeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .read_fifo = tusb_read_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .write_fifo = tusb_write_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #ifdef CONFIG_USB_TUSB_OMAP_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .dma_init = tusb_dma_controller_create,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .dma_exit = tusb_dma_controller_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .enable = tusb_musb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .disable = tusb_musb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .set_mode = tusb_musb_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .try_idle = tusb_musb_try_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .vbus_status = tusb_musb_vbus_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .set_vbus = tusb_musb_set_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static const struct platform_device_info tusb_dev_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .name = "musb-hdrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .id = PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int tusb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct resource musb_resources[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct platform_device *musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct tusb6010_glue *glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct platform_device_info pinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (!glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) glue->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pdata->platform_ops = &tusb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) usb_phy_generic_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) platform_set_drvdata(pdev, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) memset(musb_resources, 0x00, sizeof(*musb_resources) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ARRAY_SIZE(musb_resources));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) musb_resources[0].name = pdev->resource[0].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) musb_resources[0].start = pdev->resource[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) musb_resources[0].end = pdev->resource[0].end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) musb_resources[0].flags = pdev->resource[0].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) musb_resources[1].name = pdev->resource[1].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) musb_resources[1].start = pdev->resource[1].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) musb_resources[1].end = pdev->resource[1].end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) musb_resources[1].flags = pdev->resource[1].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) musb_resources[2].name = pdev->resource[2].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) musb_resources[2].start = pdev->resource[2].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) musb_resources[2].end = pdev->resource[2].end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) musb_resources[2].flags = pdev->resource[2].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) pinfo = tusb_dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) pinfo.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) pinfo.res = musb_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) pinfo.num_res = ARRAY_SIZE(musb_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) pinfo.data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) pinfo.size_data = sizeof(*pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) glue->musb = musb = platform_device_register_full(&pinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (IS_ERR(musb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret = PTR_ERR(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static int tusb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct tusb6010_glue *glue = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) platform_device_unregister(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) usb_phy_generic_unregister(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static struct platform_driver tusb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .probe = tusb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .remove = tusb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .name = "musb-tusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) module_platform_driver(tusb_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags