^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Allwinner sun4i MUSB Glue Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on code from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/extcon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy-sun4i-usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/soc/sunxi/sunxi_sram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/musb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/usb/usb_phy_generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Register offsets, note sunxi musb has a different layout then most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * musb implementations, we translate the layout in musb_readb & friends.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUNXI_MUSB_POWER 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUNXI_MUSB_DEVCTL 0x0041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUNXI_MUSB_INDEX 0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUNXI_MUSB_VEND0 0x0043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUNXI_MUSB_INTRTX 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUNXI_MUSB_INTRRX 0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUNXI_MUSB_INTRTXE 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUNXI_MUSB_INTRRXE 0x004a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUNXI_MUSB_INTRUSB 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUNXI_MUSB_INTRUSBE 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUNXI_MUSB_FRAME 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUNXI_MUSB_TXFIFOSZ 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUNXI_MUSB_TXFIFOADD 0x0092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUNXI_MUSB_RXFIFOSZ 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUNXI_MUSB_RXFIFOADD 0x0096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUNXI_MUSB_FADDR 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUNXI_MUSB_TXFUNCADDR 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUNXI_MUSB_TXHUBADDR 0x009a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUNXI_MUSB_TXHUBPORT 0x009b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUNXI_MUSB_RXFUNCADDR 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUNXI_MUSB_RXHUBADDR 0x009e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUNXI_MUSB_RXHUBPORT 0x009f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUNXI_MUSB_CONFIGDATA 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* VEND0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SUNXI_MUSB_VEND0_PIO_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SUNXI_MUSB_FL_ENABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SUNXI_MUSB_FL_HOSTMODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SUNXI_MUSB_FL_HOSTMODE_PEND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SUNXI_MUSB_FL_VBUS_ON 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SUNXI_MUSB_FL_PHY_ON 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SUNXI_MUSB_FL_HAS_SRAM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SUNXI_MUSB_FL_HAS_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SUNXI_MUSB_FL_NO_CONFIGDATA 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SUNXI_MUSB_FL_PHY_MODE_PEND 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Our read/write methods need access and do not get passed in a musb ref :| */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct musb *sunxi_musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct sunxi_glue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct musb *musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct platform_device *musb_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct platform_device *usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct usb_phy *xceiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum phy_mode phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct extcon_dev *extcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct notifier_block host_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* phy_power_on / off may sleep, so we use a workqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void sunxi_musb_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool vbus_on, phy_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct musb *musb = glue->musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 devctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) devctl |= MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MUSB_DEV_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) devctl &= ~MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (phy_on != vbus_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (vbus_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) phy_power_on(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) phy_power_off(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) phy_set_mode(glue->phy, glue->phy_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) schedule_work(&glue->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void sunxi_musb_pre_root_reset_end(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) sun4i_usb_phy_set_squelch_detect(glue->phy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void sunxi_musb_post_root_reset_end(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sun4i_usb_phy_set_squelch_detect(glue->phy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct musb *musb = __hci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (musb->int_usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* ep0 FADDR must be 0 when (re)entering peripheral mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) musb_ep_select(musb->mregs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) musb_writeb(musb->mregs, MUSB_FADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (musb->int_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (musb->int_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) musb_interrupt(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int sunxi_musb_host_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) schedule_work(&glue->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int sunxi_musb_init(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sunxi_musb = musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) musb->phy = glue->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) musb->xceiv = glue->xceiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = sunxi_sram_claim(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = clk_prepare_enable(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto error_sram_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = reset_control_deassert(glue->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto error_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Register notifier before calling phy_init() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = devm_extcon_register_notifier(glue->dev, glue->extcon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) EXTCON_USB_HOST, &glue->host_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto error_reset_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = phy_init(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto error_reset_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) musb->isr = sunxi_musb_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pm_runtime_get(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) error_reset_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reset_control_assert(glue->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) error_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk_disable_unprepare(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) error_sram_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sunxi_sram_release(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int sunxi_musb_exit(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pm_runtime_put(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cancel_work_sync(&glue->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) phy_power_off(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) phy_exit(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) reset_control_assert(glue->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk_disable_unprepare(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sunxi_sram_release(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) devm_usb_put_phy(glue->dev, glue->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void sunxi_musb_enable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) glue->musb = musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* musb_core does not call us in a balanced manner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) schedule_work(&glue->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void sunxi_musb_disable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void sunxi_musb_dma_controller_destroy(struct dma_controller *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int sunxi_musb_set_mode(struct musb *musb, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) enum phy_mode new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case MUSB_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) new_mode = PHY_MODE_USB_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case MUSB_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) new_mode = PHY_MODE_USB_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case MUSB_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) new_mode = PHY_MODE_USB_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "Error requested mode not supported by this kernel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (glue->phy_mode == new_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (musb->port_mode != MUSB_OTG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "Error changing modes is only supported in dual role mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (musb->port1_status & USB_PORT_STAT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) musb_root_disconnect(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * phy_set_mode may sleep, and we're called with a spinlock held,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * so let sunxi_musb_work deal with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) glue->phy_mode = new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) schedule_work(&glue->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int sunxi_musb_recover(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Schedule a phy_set_mode with the current glue->phy_mode value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * this will force end the current session.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) schedule_work(&glue->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * sunxi musb register layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * 0x00 - 0x17 fifo regs, 1 long per fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * 0x40 - 0x57 generic control regs (power - frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * 0x90 - 0x97 fifo control regs (indexed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * 0x98 - 0x9f multipoint / busctl regs (indexed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * 0xc0 configdata reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static u32 sunxi_musb_fifo_offset(u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return (epnum * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) WARN_ONCE(offset != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "sunxi_musb_ep_offset called with non 0 offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0x80; /* indexed, so ignore epnum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return SUNXI_MUSB_TXFUNCADDR + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static u8 sunxi_musb_readb(void __iomem *addr, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct sunxi_glue *glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (addr == sunxi_musb->mregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* generic control or fifo control reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case MUSB_FADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return readb(addr + SUNXI_MUSB_FADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case MUSB_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return readb(addr + SUNXI_MUSB_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case MUSB_INTRUSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return readb(addr + SUNXI_MUSB_INTRUSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case MUSB_INTRUSBE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return readb(addr + SUNXI_MUSB_INTRUSBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case MUSB_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return readb(addr + SUNXI_MUSB_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case MUSB_TESTMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0; /* No testmode on sunxi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case MUSB_DEVCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return readb(addr + SUNXI_MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case MUSB_TXFIFOSZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return readb(addr + SUNXI_MUSB_TXFIFOSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case MUSB_RXFIFOSZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return readb(addr + SUNXI_MUSB_RXFIFOSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) glue = dev_get_drvdata(sunxi_musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* A33 saves a reg, and we get to hardcode this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) &glue->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0xde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return readb(addr + SUNXI_MUSB_CONFIGDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Offset for these is fixed by sunxi_musb_busctl_offset() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case SUNXI_MUSB_TXFUNCADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case SUNXI_MUSB_TXHUBADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case SUNXI_MUSB_TXHUBPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case SUNXI_MUSB_RXFUNCADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case SUNXI_MUSB_RXHUBADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case SUNXI_MUSB_RXHUBPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* multipoint / busctl reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return readb(addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "Error unknown readb offset %u\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else if (addr == (sunxi_musb->mregs + 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* ep control reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* sunxi has a 2 byte hole before the txtype register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (offset >= MUSB_TXTYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) offset += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return readb(addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "Error unknown readb at 0x%x bytes offset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) (int)(addr - sunxi_musb->mregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (addr == sunxi_musb->mregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* generic control or fifo control reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case MUSB_FADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return writeb(data, addr + SUNXI_MUSB_FADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case MUSB_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return writeb(data, addr + SUNXI_MUSB_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case MUSB_INTRUSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return writeb(data, addr + SUNXI_MUSB_INTRUSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case MUSB_INTRUSBE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case MUSB_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return writeb(data, addr + SUNXI_MUSB_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case MUSB_TESTMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_warn(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "sunxi-musb does not have testmode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case MUSB_DEVCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return writeb(data, addr + SUNXI_MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case MUSB_TXFIFOSZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case MUSB_RXFIFOSZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Offset for these is fixed by sunxi_musb_busctl_offset() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case SUNXI_MUSB_TXFUNCADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case SUNXI_MUSB_TXHUBADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case SUNXI_MUSB_TXHUBPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case SUNXI_MUSB_RXFUNCADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case SUNXI_MUSB_RXHUBADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case SUNXI_MUSB_RXHUBPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* multipoint / busctl reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return writeb(data, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "Error unknown writeb offset %u\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } else if (addr == (sunxi_musb->mregs + 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* ep control reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (offset >= MUSB_TXTYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) offset += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return writeb(data, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "Error unknown writeb at 0x%x bytes offset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) (int)(addr - sunxi_musb->mregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static u16 sunxi_musb_readw(void __iomem *addr, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (addr == sunxi_musb->mregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* generic control or fifo control reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case MUSB_INTRTX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return readw(addr + SUNXI_MUSB_INTRTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case MUSB_INTRRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return readw(addr + SUNXI_MUSB_INTRRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case MUSB_INTRTXE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return readw(addr + SUNXI_MUSB_INTRTXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case MUSB_INTRRXE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return readw(addr + SUNXI_MUSB_INTRRXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case MUSB_FRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return readw(addr + SUNXI_MUSB_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case MUSB_TXFIFOADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return readw(addr + SUNXI_MUSB_TXFIFOADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case MUSB_RXFIFOADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return readw(addr + SUNXI_MUSB_RXFIFOADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case MUSB_HWVERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0; /* sunxi musb version is not known */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "Error unknown readw offset %u\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) } else if (addr == (sunxi_musb->mregs + 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* ep control reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return readw(addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_err(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "Error unknown readw at 0x%x bytes offset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) (int)(addr - sunxi_musb->mregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (addr == sunxi_musb->mregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* generic control or fifo control reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case MUSB_INTRTX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return writew(data, addr + SUNXI_MUSB_INTRTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case MUSB_INTRRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return writew(data, addr + SUNXI_MUSB_INTRRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case MUSB_INTRTXE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return writew(data, addr + SUNXI_MUSB_INTRTXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case MUSB_INTRRXE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return writew(data, addr + SUNXI_MUSB_INTRRXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case MUSB_FRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return writew(data, addr + SUNXI_MUSB_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case MUSB_TXFIFOADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case MUSB_RXFIFOADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_err(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "Error unknown writew offset %u\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else if (addr == (sunxi_musb->mregs + 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* ep control reg access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return writew(data, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(sunxi_musb->controller->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) "Error unknown writew at 0x%x bytes offset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) (int)(addr - sunxi_musb->mregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct musb_platform_ops sunxi_musb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .quirks = MUSB_INDEXED_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .init = sunxi_musb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .exit = sunxi_musb_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .enable = sunxi_musb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .disable = sunxi_musb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .fifo_offset = sunxi_musb_fifo_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .ep_offset = sunxi_musb_ep_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .busctl_offset = sunxi_musb_busctl_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .readb = sunxi_musb_readb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .writeb = sunxi_musb_writeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .readw = sunxi_musb_readw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .writew = sunxi_musb_writew,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .dma_init = sunxi_musb_dma_controller_create,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .dma_exit = sunxi_musb_dma_controller_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .set_mode = sunxi_musb_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .recover = sunxi_musb_recover,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .set_vbus = sunxi_musb_set_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .post_root_reset_end = sunxi_musb_post_root_reset_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Allwinner OTG supports up to 5 endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SUNXI_MUSB_MAX_EP_NUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SUNXI_MUSB_RAM_BITS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* H3/V3s OTG supports only 4 endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define SUNXI_MUSB_MAX_EP_NUM_H3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct musb_hdrc_config sunxi_musb_hdrc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .fifo_cfg = sunxi_musb_mode_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .multipoint = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .dyn_fifo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .num_eps = SUNXI_MUSB_MAX_EP_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .ram_bits = SUNXI_MUSB_RAM_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static struct musb_hdrc_config sunxi_musb_hdrc_config_h3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .fifo_cfg = sunxi_musb_mode_cfg_h3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .multipoint = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .dyn_fifo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .ram_bits = SUNXI_MUSB_RAM_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int sunxi_musb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct musb_hdrc_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct platform_device_info pinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct sunxi_glue *glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(&pdev->dev, "Error no device tree node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) memset(&pdata, 0, sizeof(pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) switch (usb_get_dr_mode(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pdata.mode = MUSB_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) glue->phy_mode = PHY_MODE_USB_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pdata.mode = MUSB_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) glue->phy_mode = PHY_MODE_USB_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #ifdef CONFIG_USB_MUSB_DUAL_ROLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case USB_DR_MODE_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pdata.mode = MUSB_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) glue->phy_mode = PHY_MODE_USB_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pdata.platform_ops = &sunxi_musb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!of_device_is_compatible(np, "allwinner,sun8i-h3-musb"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pdata.config = &sunxi_musb_hdrc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pdata.config = &sunxi_musb_hdrc_config_h3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) glue->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) INIT_WORK(&glue->work, sunxi_musb_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) glue->host_nb.notifier_call = sunxi_musb_host_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) glue->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (IS_ERR(glue->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_err(&pdev->dev, "Error getting clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PTR_ERR(glue->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return PTR_ERR(glue->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) glue->rst = devm_reset_control_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (IS_ERR(glue->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (PTR_ERR(glue->rst) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_err(&pdev->dev, "Error getting reset %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PTR_ERR(glue->rst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return PTR_ERR(glue->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (IS_ERR(glue->extcon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_err(&pdev->dev, "Invalid or missing extcon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return PTR_ERR(glue->extcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) glue->phy = devm_phy_get(&pdev->dev, "usb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (IS_ERR(glue->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_err(&pdev->dev, "Error getting phy %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PTR_ERR(glue->phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return PTR_ERR(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) glue->usb_phy = usb_phy_generic_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (IS_ERR(glue->usb_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PTR_ERR(glue->usb_phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return PTR_ERR(glue->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (IS_ERR(glue->xceiv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = PTR_ERR(glue->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) goto err_unregister_usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) platform_set_drvdata(pdev, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) memset(&pinfo, 0, sizeof(pinfo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pinfo.name = "musb-hdrc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pinfo.id = PLATFORM_DEVID_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pinfo.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pinfo.fwnode = of_fwnode_handle(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) pinfo.of_node_reused = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pinfo.res = pdev->resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pinfo.num_res = pdev->num_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) pinfo.data = &pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pinfo.size_data = sizeof(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) glue->musb_pdev = platform_device_register_full(&pinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (IS_ERR(glue->musb_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = PTR_ERR(glue->musb_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) goto err_unregister_usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) err_unregister_usb_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) usb_phy_generic_unregister(glue->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int sunxi_musb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct sunxi_glue *glue = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct platform_device *usb_phy = glue->usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) platform_device_unregister(glue->musb_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) usb_phy_generic_unregister(usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const struct of_device_id sunxi_musb_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { .compatible = "allwinner,sun4i-a10-musb", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { .compatible = "allwinner,sun6i-a31-musb", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { .compatible = "allwinner,sun8i-a33-musb", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { .compatible = "allwinner,sun8i-h3-musb", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MODULE_DEVICE_TABLE(of, sunxi_musb_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static struct platform_driver sunxi_musb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .probe = sunxi_musb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .remove = sunxi_musb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .name = "musb-sunxi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .of_match_table = sunxi_musb_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) module_platform_driver(sunxi_musb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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