Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2005-2006 by Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __MUSB_OMAP243X_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __MUSB_OMAP243X_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/platform_data/usb-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * OMAP2430-specific definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OTG_REVISION		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OTG_SYSCONFIG		0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #	define	MIDLEMODE	12	/* bit position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #	define	FORCESTDBY		(0 << MIDLEMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #	define	NOSTDBY			(1 << MIDLEMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #	define	SMARTSTDBY		(2 << MIDLEMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #	define	SIDLEMODE		3	/* bit position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #	define	FORCEIDLE		(0 << SIDLEMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #	define	NOIDLE			(1 << SIDLEMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #	define	SMARTIDLE		(2 << SIDLEMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #	define	ENABLEWAKEUP		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #	define	SOFTRST			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #	define	AUTOIDLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OTG_SYSSTATUS		0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #	define	RESETDONE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OTG_INTERFSEL		0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #	define	EXTCP			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #	define	PHYSEL			0	/* bit position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #	define	UTMI_8BIT		(0 << PHYSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #	define	ULPI_12PIN		(1 << PHYSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #	define	ULPI_8PIN		(2 << PHYSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OTG_SIMENABLE		0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #	define	TM1			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OTG_FORCESTDBY		0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #	define	ENABLEFORCE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif	/* __MUSB_OMAP243X_H__ */