Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * MUSB OTG driver register defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2005 Mentor Graphics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2005-2006 by Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2006-2007 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __MUSB_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __MUSB_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MUSB_EP0_FIFOSIZE	64	/* This is non-configurable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * MUSB Register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* POWER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MUSB_POWER_ISOUPDATE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MUSB_POWER_SOFTCONN	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MUSB_POWER_HSENAB	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MUSB_POWER_HSMODE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MUSB_POWER_RESET	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MUSB_POWER_RESUME	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MUSB_POWER_SUSPENDM	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MUSB_POWER_ENSUSPEND	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* INTRUSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MUSB_INTR_SUSPEND	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MUSB_INTR_RESUME	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MUSB_INTR_RESET		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MUSB_INTR_BABBLE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MUSB_INTR_SOF		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MUSB_INTR_CONNECT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MUSB_INTR_DISCONNECT	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MUSB_INTR_SESSREQ	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MUSB_INTR_VBUSERROR	0x80	/* For SESSION end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* DEVCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MUSB_DEVCTL_BDEVICE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MUSB_DEVCTL_FSDEV	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MUSB_DEVCTL_LSDEV	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MUSB_DEVCTL_VBUS	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MUSB_DEVCTL_VBUS_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MUSB_DEVCTL_HM		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MUSB_DEVCTL_HR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MUSB_DEVCTL_SESSION	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* BABBLE_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MUSB_BABBLE_FORCE_TXIDLE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MUSB_BABBLE_SW_SESSION_CTRL	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MUSB_BABBLE_STUCK_J		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MUSB_BABBLE_RCV_DISABLE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* MUSB ULPI VBUSCONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MUSB_ULPI_USE_EXTVBUS	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MUSB_ULPI_USE_EXTVBUSIND 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* ULPI_REG_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MUSB_ULPI_REG_REQ	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MUSB_ULPI_REG_CMPLT	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MUSB_ULPI_RDN_WR	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* TESTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MUSB_TEST_FORCE_HOST	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MUSB_TEST_FIFO_ACCESS	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MUSB_TEST_FORCE_FS	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MUSB_TEST_FORCE_HS	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MUSB_TEST_PACKET	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MUSB_TEST_K		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MUSB_TEST_J		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MUSB_TEST_SE0_NAK	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MUSB_FIFOSZ_DPB	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Allocation size (8, 16, 32, ... 4096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MUSB_FIFOSZ_SIZE	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* CSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MUSB_CSR0_FLUSHFIFO	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MUSB_CSR0_TXPKTRDY	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MUSB_CSR0_RXPKTRDY	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* CSR0 in Peripheral mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MUSB_CSR0_P_SVDSETUPEND	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MUSB_CSR0_P_SVDRXPKTRDY	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MUSB_CSR0_P_SENDSTALL	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MUSB_CSR0_P_SETUPEND	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MUSB_CSR0_P_DATAEND	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MUSB_CSR0_P_SENTSTALL	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* CSR0 in Host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MUSB_CSR0_H_DIS_PING		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MUSB_CSR0_H_WR_DATATOGGLE	0x0400	/* Set to allow setting: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MUSB_CSR0_H_DATATOGGLE		0x0200	/* Data toggle control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MUSB_CSR0_H_NAKTIMEOUT		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MUSB_CSR0_H_STATUSPKT		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MUSB_CSR0_H_REQPKT		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MUSB_CSR0_H_ERROR		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MUSB_CSR0_H_SETUPPKT		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MUSB_CSR0_H_RXSTALL		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MUSB_CSR0_P_WZC_BITS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	(MUSB_CSR0_P_SENTSTALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MUSB_CSR0_H_WZC_BITS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	(MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	| MUSB_CSR0_RXPKTRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* TxType/RxType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MUSB_TYPE_SPEED		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MUSB_TYPE_SPEED_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MUSB_TYPE_PROTO		0x30	/* Implicitly zero for ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MUSB_TYPE_PROTO_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MUSB_TYPE_REMOTE_END	0xf	/* Implicitly zero for ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* CONFIGDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MUSB_CONFIGDATA_MPRXE		0x80	/* Auto bulk pkt combining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MUSB_CONFIGDATA_MPTXE		0x40	/* Auto bulk pkt splitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MUSB_CONFIGDATA_BIGENDIAN	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MUSB_CONFIGDATA_HBRXE		0x10	/* HB-ISO for RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MUSB_CONFIGDATA_HBTXE		0x08	/* HB-ISO for TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MUSB_CONFIGDATA_DYNFIFO		0x04	/* Dynamic FIFO sizing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MUSB_CONFIGDATA_SOFTCONE	0x02	/* SoftConnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MUSB_CONFIGDATA_UTMIDW		0x01	/* Data width 0/1 => 8/16bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* TXCSR in Peripheral and Host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MUSB_TXCSR_AUTOSET		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MUSB_TXCSR_DMAENAB		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MUSB_TXCSR_FRCDATATOG		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MUSB_TXCSR_DMAMODE		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MUSB_TXCSR_CLRDATATOG		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MUSB_TXCSR_FLUSHFIFO		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MUSB_TXCSR_FIFONOTEMPTY		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MUSB_TXCSR_TXPKTRDY		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* TXCSR in Peripheral mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MUSB_TXCSR_P_ISO		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MUSB_TXCSR_P_INCOMPTX		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MUSB_TXCSR_P_SENTSTALL		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MUSB_TXCSR_P_SENDSTALL		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MUSB_TXCSR_P_UNDERRUN		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* TXCSR in Host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MUSB_TXCSR_H_WR_DATATOGGLE	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MUSB_TXCSR_H_DATATOGGLE		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MUSB_TXCSR_H_NAKTIMEOUT		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MUSB_TXCSR_H_RXSTALL		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MUSB_TXCSR_H_ERROR		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MUSB_TXCSR_P_WZC_BITS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	(MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	| MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MUSB_TXCSR_H_WZC_BITS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	(MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	| MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* RXCSR in Peripheral and Host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MUSB_RXCSR_AUTOCLEAR		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MUSB_RXCSR_DMAENAB		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MUSB_RXCSR_DISNYET		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MUSB_RXCSR_PID_ERR		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MUSB_RXCSR_DMAMODE		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MUSB_RXCSR_INCOMPRX		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MUSB_RXCSR_CLRDATATOG		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MUSB_RXCSR_FLUSHFIFO		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MUSB_RXCSR_DATAERROR		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MUSB_RXCSR_FIFOFULL		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MUSB_RXCSR_RXPKTRDY		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* RXCSR in Peripheral mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MUSB_RXCSR_P_ISO		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MUSB_RXCSR_P_SENTSTALL		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MUSB_RXCSR_P_SENDSTALL		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MUSB_RXCSR_P_OVERRUN		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* RXCSR in Host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MUSB_RXCSR_H_AUTOREQ		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MUSB_RXCSR_H_WR_DATATOGGLE	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MUSB_RXCSR_H_DATATOGGLE		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MUSB_RXCSR_H_RXSTALL		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MUSB_RXCSR_H_REQPKT		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MUSB_RXCSR_H_ERROR		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MUSB_RXCSR_P_WZC_BITS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	(MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	| MUSB_RXCSR_RXPKTRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MUSB_RXCSR_H_WZC_BITS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	(MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	| MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* HUBADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MUSB_HUBADDR_MULTI_TT		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * Common USB registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MUSB_FADDR		0x00	/* 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MUSB_POWER		0x01	/* 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MUSB_INTRTX		0x02	/* 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MUSB_INTRRX		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MUSB_INTRTXE		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MUSB_INTRRXE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MUSB_INTRUSB		0x0A	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MUSB_INTRUSBE		0x0B	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MUSB_FRAME		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MUSB_INDEX		0x0E	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MUSB_TESTMODE		0x0F	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * Additional Control Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MUSB_DEVCTL		0x60	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MUSB_BABBLE_CTL		0x61	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* These are always controlled through the INDEX register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MUSB_TXFIFOSZ		0x62	/* 8-bit (see masks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MUSB_RXFIFOSZ		0x63	/* 8-bit (see masks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MUSB_TXFIFOADD		0x64	/* 16-bit offset shifted right 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MUSB_RXFIFOADD		0x66	/* 16-bit offset shifted right 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MUSB_HWVERS		0x6C	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MUSB_ULPI_BUSCONTROL	0x70	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MUSB_ULPI_INT_MASK	0x72	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MUSB_ULPI_INT_SRC	0x73	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MUSB_ULPI_REG_DATA	0x74	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MUSB_ULPI_REG_ADDR	0x75	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MUSB_ULPI_REG_CONTROL	0x76	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MUSB_ULPI_RAW_DATA	0x77	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MUSB_EPINFO		0x78	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MUSB_RAMINFO		0x79	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MUSB_LINKINFO		0x7a	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MUSB_VPLEN		0x7b	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MUSB_HS_EOF1		0x7c	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MUSB_FS_EOF1		0x7d	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MUSB_LS_EOF1		0x7e	/* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Offsets to endpoint registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MUSB_TXMAXP		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MUSB_TXCSR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MUSB_CSR0		MUSB_TXCSR	/* Re-used for EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MUSB_RXMAXP		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MUSB_RXCSR		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MUSB_RXCOUNT		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MUSB_COUNT0		MUSB_RXCOUNT	/* Re-used for EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MUSB_TXTYPE		0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MUSB_TYPE0		MUSB_TXTYPE	/* Re-used for EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MUSB_TXINTERVAL		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MUSB_NAKLIMIT0		MUSB_TXINTERVAL	/* Re-used for EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MUSB_RXTYPE		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MUSB_RXINTERVAL		0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MUSB_FIFOSIZE		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MUSB_TXCSR_MODE			0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* "bus control"/target registers, for host side multipoint (external hubs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MUSB_TXFUNCADDR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MUSB_TXHUBADDR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MUSB_TXHUBPORT		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MUSB_RXFUNCADDR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MUSB_RXHUBADDR		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MUSB_RXHUBPORT		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static inline u8 musb_read_configdata(void __iomem *mbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	musb_writeb(mbase, MUSB_INDEX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static inline void musb_write_rxfunaddr(struct musb *musb, u8 epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		u8 qh_addr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	musb_writeb(musb->mregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		    musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		    qh_addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static inline void musb_write_rxhubaddr(struct musb *musb, u8 epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		u8 qh_h_addr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			qh_h_addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static inline void musb_write_rxhubport(struct musb *musb, u8 epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		u8 qh_h_port_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBPORT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			qh_h_port_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline void musb_write_txfunaddr(struct musb *musb, u8 epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		u8 qh_addr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	musb_writeb(musb->mregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		    musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		    qh_addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static inline void musb_write_txhubaddr(struct musb *musb, u8 epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		u8 qh_addr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			qh_addr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static inline void musb_write_txhubport(struct musb *musb, u8 epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		u8 qh_h_port_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBPORT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			qh_h_port_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static inline u8 musb_read_rxfunaddr(struct musb *musb, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	return musb_readb(musb->mregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			  musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static inline u8 musb_read_rxhubaddr(struct musb *musb, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return musb_readb(musb->mregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			  musb->io.busctl_offset(epnum, MUSB_RXHUBADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline u8 musb_read_rxhubport(struct musb *musb, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return musb_readb(musb->mregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			  musb->io.busctl_offset(epnum, MUSB_RXHUBPORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static inline u8 musb_read_txfunaddr(struct musb *musb, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return musb_readb(musb->mregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			  musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static inline u8 musb_read_txhubaddr(struct musb *musb, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return musb_readb(musb->mregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			  musb->io.busctl_offset(epnum, MUSB_TXHUBADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return musb_readb(musb->mregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			  musb->io.busctl_offset(epnum, MUSB_TXHUBPORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif	/* __MUSB_REGS_H__ */