^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Texas Instruments DSPS platforms "glue layer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012, by Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the am35x "glue layer" code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is part of the Inventra Controller Driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * musb_dsps.c will be a common file for all the TI DSPS platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * For now only ti81x is using this and in future davinci.c, am35x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * da8xx.c would be merged to this file after testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/usb_phy_generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/usb-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/usb/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct of_device_id musb_dsps_of_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * DSPS musb wrapper register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * musb ips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct dsps_musb_wrapper {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u16 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u16 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u16 epintr_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u16 epintr_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u16 epintr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u16 coreintr_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u16 coreintr_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 coreintr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 phy_utmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 tx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 rx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* bit positions for control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned reset:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* bit positions for interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned usb_shift:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 usb_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 usb_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned drvvbus:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned txep_shift:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 txep_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 txep_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned rxep_shift:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 rxep_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 rxep_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* bit positions for phy_utmi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned otg_disable:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* bit positions for mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned iddig:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned iddig_mux:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* miscellaneous stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned poll_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * register shadow for suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct dsps_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 epintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 coreintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 phy_utmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 tx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 rx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * DSPS glue structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct dsps_glue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct platform_device *musb; /* child musb pdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int vbus_irq; /* optional vbus irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long last_timer; /* last timer data for each instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bool sw_babble_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *usbss_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct dsps_context context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct debugfs_regset32 regset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct dentry *dbgfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct debugfs_reg32 dsps_musb_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { "revision", 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { "control", 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { "status", 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { "eoi", 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { "intr0_stat", 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { "intr1_stat", 0x34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { "intr0_set", 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { "intr1_set", 0x3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { "txmode", 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { "rxmode", 0x74 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { "autoreq", 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { "srpfixtime", 0xd4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { "tdown", 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { "phy_utmi", 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { "mode", 0xe8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void dsps_mod_timer(struct dsps_glue *glue, int wait_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct musb *musb = platform_get_drvdata(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (wait_ms < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) wait = msecs_to_jiffies(glue->wrp->poll_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) wait = msecs_to_jiffies(wait_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mod_timer(&musb->dev_timer, jiffies + wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * If no vbus irq from the PMIC is configured, we need to poll VBUS status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void dsps_mod_timer_optional(struct dsps_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (glue->vbus_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dsps_mod_timer(glue, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* USBSS / USB AM335x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define USBSS_IRQ_STATUS 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USBSS_IRQ_ENABLER 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define USBSS_IRQ_CLEARR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define USBSS_IRQ_PD_COMP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * dsps_musb_enable - enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void dsps_musb_enable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct dsps_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __iomem *reg_base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 epmask, coremask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Workaround: setup IRQs through both register sets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) musb_writel(reg_base, wrp->epintr_set, epmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) musb_writel(reg_base, wrp->coreintr_set, coremask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * start polling for runtime PM active and idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * and for ID change in dual-role idle mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dsps_mod_timer(glue, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * dsps_musb_disable - disable HDRC and flush interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void dsps_musb_disable(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct dsps_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void __iomem *reg_base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) musb_writel(reg_base, wrp->epintr_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) wrp->txep_bitmap | wrp->rxep_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) del_timer_sync(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Caller must take musb->lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int dsps_check_status(struct musb *musb, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void __iomem *mregs = musb->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct dsps_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 devctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int skip_session = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (glue->vbus_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) del_timer(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * We poll because DSPS IP's won't expose several OTG-critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * status change events (from the transceiver) otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) devctl = musb_readb(mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) usb_otg_state_string(musb->xceiv->otg->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case OTG_STATE_A_WAIT_VRISE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (musb->port_mode == MUSB_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dsps_mod_timer_optional(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* keep VBUS on for host-only mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (musb->port_mode == MUSB_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dsps_mod_timer_optional(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) skip_session = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case OTG_STATE_A_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case OTG_STATE_B_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!glue->vbus_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (devctl & MUSB_DEVCTL_BDEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MUSB_DEV_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) musb->xceiv->otg->state = OTG_STATE_A_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (musb->port_mode == MUSB_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) skip_session = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) musb_writeb(mregs, MUSB_DEVCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUSB_DEVCTL_SESSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dsps_mod_timer_optional(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case OTG_STATE_A_WAIT_VFALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) musb_writel(musb->ctrl_base, wrp->coreintr_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MUSB_INTR_VBUSERROR << wrp->usb_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void otg_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct musb *musb = from_timer(musb, t, dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) err = pm_runtime_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if ((err != -EINPROGRESS) && err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(dev, "Poll could not pm_runtime_get: %i\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) err = musb_queue_resume_work(musb, dsps_check_status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(dev, "%s resume work: %i\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void dsps_musb_clear_ep_rxintr(struct musb *musb, int epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 epintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* musb->lock might already been held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) epintr = (1 << epnum) << wrp->rxep_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) musb_writel(musb->ctrl_base, wrp->epintr_status, epintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static irqreturn_t dsps_interrupt(int irq, void *hci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct musb *musb = hci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void __iomem *reg_base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct dsps_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 epintr, usbintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Get endpoint interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) epintr = musb_readl(reg_base, wrp->epintr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (epintr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) musb_writel(reg_base, wrp->epintr_status, epintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Get usb core interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) usbintr = musb_readl(reg_base, wrp->coreintr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!usbintr && !epintr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (usbintr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) musb_writel(reg_base, wrp->coreintr_status, usbintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) usbintr, epintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int drvvbus = musb_readl(reg_base, wrp->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void __iomem *mregs = musb->mregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) err = musb->int_usb & MUSB_INTR_VBUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * The Mentor core doesn't debounce VBUS as needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * to cope with device connect current spikes. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * means it's not uncommon for bus-powered devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * to get VBUS errors during enumeration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * This is a workaround, but newer RTL from Mentor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * seems to allow a better one: "re"-starting sessions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * without waiting for VBUS to stop registering in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * devctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) musb->int_usb &= ~MUSB_INTR_VBUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dsps_mod_timer_optional(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) WARNING("VBUS error workaround (delay coming)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } else if (drvvbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dsps_mod_timer_optional(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) musb->is_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MUSB_DEV_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* NOTE: this must complete power-on within 100 ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) drvvbus ? "on" : "off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) usb_otg_state_string(musb->xceiv->otg->state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) err ? " ERROR" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (musb->int_tx || musb->int_rx || musb->int_usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret |= musb_interrupt(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Poll for ID change and connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case OTG_STATE_B_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dsps_mod_timer_optional(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) char buf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sprintf(buf, "%s.dsps", dev_name(musb->controller));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) root = debugfs_create_dir(buf, usb_debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) glue->dbgfs_root = root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) glue->regset.regs = dsps_musb_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) glue->regset.base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int dsps_musb_init(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct dsps_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct platform_device *parent = to_platform_device(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 rev, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) reg_base = devm_ioremap_resource(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (IS_ERR(reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) musb->ctrl_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* NOP driver needs change if supporting dual instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (IS_ERR(musb->xceiv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return PTR_ERR(musb->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) musb->phy = devm_phy_get(dev->parent, "usb2-phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Returns zero if e.g. not clocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rev = musb_readl(reg_base, wrp->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (IS_ERR(musb->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) musb->phy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ret = phy_init(musb->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = phy_power_on(musb->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) phy_exit(musb->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) timer_setup(&musb->dev_timer, otg_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Reset the musb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) musb_writel(reg_base, wrp->control, (1 << wrp->reset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) musb->isr = dsps_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* reset the otgdisable bit, needed for host mode to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val = musb_readl(reg_base, wrp->phy_utmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val &= ~(1 << wrp->otg_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) musb_writel(musb->ctrl_base, wrp->phy_utmi, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Check whether the dsps version has babble control enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * In latest silicon revision the babble control logic is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * logic enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) val = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (val & MUSB_BABBLE_RCV_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) glue->sw_babble_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) val |= MUSB_BABBLE_SW_SESSION_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dsps_mod_timer(glue, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return dsps_musb_dbg_init(musb, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int dsps_musb_exit(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct dsps_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) del_timer_sync(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) phy_power_off(musb->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) phy_exit(musb->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) debugfs_remove_recursive(glue->dbgfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int dsps_musb_set_mode(struct musb *musb, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct dsps_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void __iomem *ctrl_base = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) reg = musb_readl(ctrl_base, wrp->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case MUSB_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) reg &= ~(1 << wrp->iddig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * if we're setting mode to host-only or device-only, we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * going to ignore whatever the PHY sends us and just force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * ID pin status by SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) reg |= (1 << wrp->iddig_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) musb_writel(ctrl_base, wrp->mode, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case MUSB_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) reg |= (1 << wrp->iddig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * if we're setting mode to host-only or device-only, we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * going to ignore whatever the PHY sends us and just force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * ID pin status by SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) reg |= (1 << wrp->iddig_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) musb_writel(ctrl_base, wrp->mode, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case MUSB_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(glue->dev, "unsupported mode %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static bool dsps_sw_babble_control(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u8 babble_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) bool session_restart = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) babble_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * check line monitor flag to check whether babble is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * due to noise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_dbg(musb->controller, "STUCK_J is %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (babble_ctl & MUSB_BABBLE_STUCK_J) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * babble is due to noise, then set transmit idle (d7 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * to resume normal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* wait till line monitor flag cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* check whether stuck_at_j bit cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (babble_ctl & MUSB_BABBLE_STUCK_J) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * real babble condition has occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * restart the controller to start the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * session again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) babble_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) session_restart = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) session_restart = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return session_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int dsps_musb_recover(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct dsps_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int session_restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (glue->sw_babble_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) session_restart = dsps_sw_babble_control(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) session_restart = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return session_restart ? 0 : -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Similar to am35x, dm81xx support only 32-bit read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void dsps_read_fifo32(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) void __iomem *fifo = hw_ep->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ioread32_rep(fifo, dst, len >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dst += len & ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) len &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Read any remaining 1 to 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 val = musb_readl(fifo, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) memcpy(dst, &val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #ifdef CONFIG_USB_TI_CPPI41_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void dsps_dma_controller_callback(struct dma_controller *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct musb *musb = c->musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) void __iomem *usbss_base = glue->usbss_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) status = musb_readl(usbss_base, USBSS_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (status & USBSS_IRQ_PD_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) musb_writel(usbss_base, USBSS_IRQ_STATUS, USBSS_IRQ_PD_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dsps_dma_controller_create(struct musb *musb, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct dma_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) void __iomem *usbss_base = glue->usbss_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) controller = cppi41_dma_controller_create(musb, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (IS_ERR_OR_NULL(controller))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) controller->dma_callback = dsps_dma_controller_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static void dsps_dma_controller_suspend(struct dsps_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) void __iomem *usbss_base = glue->usbss_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void dsps_dma_controller_resume(struct dsps_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) void __iomem *usbss_base = glue->usbss_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #else /* CONFIG_USB_TI_CPPI41_DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void dsps_dma_controller_suspend(struct dsps_glue *glue) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void dsps_dma_controller_resume(struct dsps_glue *glue) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #endif /* CONFIG_USB_TI_CPPI41_DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static struct musb_platform_ops dsps_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .quirks = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .init = dsps_musb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .exit = dsps_musb_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #ifdef CONFIG_USB_TI_CPPI41_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .dma_init = dsps_dma_controller_create,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .dma_exit = cppi41_dma_controller_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .enable = dsps_musb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .disable = dsps_musb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .set_mode = dsps_musb_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .recover = dsps_musb_recover,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .clear_ep_rxintr = dsps_musb_clear_ep_rxintr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static u64 musb_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int get_int_prop(struct device_node *dn, const char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = of_property_read_u32(dn, s, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int dsps_create_musb_pdev(struct dsps_glue *glue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct platform_device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct musb_hdrc_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct resource resources[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct device *dev = &parent->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct musb_hdrc_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct platform_device *musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct device_node *dn = parent->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) memset(resources, 0, sizeof(resources));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_err(dev, "failed to get memory.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) resources[0] = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_err(dev, "failed to get irq.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) resources[1] = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* allocate the child platform device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) musb = platform_device_alloc("musb-hdrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) (resources[0].start & 0xFFF) == 0x400 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!musb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_err(dev, "failed to allocate musb device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) musb->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) musb->dev.dma_mask = &musb_dmamask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) musb->dev.coherent_dma_mask = musb_dmamask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) device_set_of_node_from_dev(&musb->dev, &parent->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) glue->musb = musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = platform_device_add_resources(musb, resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ARRAY_SIZE(resources));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_err(dev, "failed to add resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (!config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pdata.config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pdata.platform_ops = &dsps_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) config->num_eps = get_int_prop(dn, "mentor,num-eps");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) config->ram_bits = get_int_prop(dn, "mentor,ram-bits");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) config->host_port_deassert_reset_at_resume = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pdata.mode = musb_get_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* DT keeps this entry in mA, musb expects it as per USB spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pdata.power = get_int_prop(dn, "mentor,power") / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = of_property_read_u32(dn, "mentor,multipoint", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!ret && val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) config->multipoint = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) config->maximum_speed = usb_get_maximum_speed(&parent->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) switch (config->maximum_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case USB_SPEED_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_warn(dev, "ignore incorrect maximum_speed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "(super-speed) setting in dts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) config->maximum_speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = platform_device_add_data(musb, &pdata, sizeof(pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(dev, "failed to add platform_data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = platform_device_add(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_err(dev, "failed to register musb device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) platform_device_put(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static irqreturn_t dsps_vbus_threaded_irq(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct dsps_glue *glue = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct musb *musb = platform_get_drvdata(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_dbg(glue->dev, "VBUS interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dsps_mod_timer(glue, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int dsps_setup_optional_vbus_irq(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct dsps_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) glue->vbus_irq = platform_get_irq_byname(pdev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (glue->vbus_irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (glue->vbus_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) glue->vbus_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) error = devm_request_threaded_irq(glue->dev, glue->vbus_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) NULL, dsps_vbus_threaded_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "vbus", glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) glue->vbus_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_dbg(glue->dev, "VBUS irq %i configured\n", glue->vbus_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int dsps_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) const struct dsps_musb_wrapper *wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct dsps_glue *glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!strcmp(pdev->name, "musb-hdrc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) match = of_match_node(musb_dsps_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_err(&pdev->dev, "fail to get matching of_match struct\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) wrp = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (of_device_is_compatible(pdev->dev.of_node, "ti,musb-dm816"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dsps_ops.read_fifo = dsps_read_fifo32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* allocate glue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) glue->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) glue->wrp = wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) glue->usbss_base = of_iomap(pdev->dev.parent->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!glue->usbss_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) platform_set_drvdata(pdev, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = dsps_create_musb_pdev(glue, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = dsps_setup_optional_vbus_irq(pdev, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto unregister_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) unregister_pdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) platform_device_unregister(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) iounmap(glue->usbss_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int dsps_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct dsps_glue *glue = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) platform_device_unregister(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) iounmap(glue->usbss_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const struct dsps_musb_wrapper am33xx_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .revision = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .control = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .status = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .epintr_set = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .epintr_clear = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .epintr_status = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .coreintr_set = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .coreintr_clear = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .coreintr_status = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .phy_utmi = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .mode = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .tx_mode = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .rx_mode = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .reset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .otg_disable = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .iddig = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .iddig_mux = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .usb_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .usb_mask = 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .usb_bitmap = (0x1ff << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .drvvbus = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .txep_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .txep_mask = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .txep_bitmap = (0xffff << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .rxep_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .rxep_mask = 0xfffe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .rxep_bitmap = (0xfffe << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .poll_timeout = 2000, /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const struct of_device_id musb_dsps_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) { .compatible = "ti,musb-am33xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .data = &am33xx_driver_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) { .compatible = "ti,musb-dm816",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .data = &am33xx_driver_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int dsps_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct dsps_glue *glue = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct musb *musb = platform_get_drvdata(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) void __iomem *mbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* This can happen if the musb device is in -EPROBE_DEFER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) del_timer_sync(&musb->dev_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) glue->context.control = musb_readl(mbase, wrp->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) glue->context.epintr = musb_readl(mbase, wrp->epintr_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) glue->context.mode = musb_readl(mbase, wrp->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dsps_dma_controller_suspend(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int dsps_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct dsps_glue *glue = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) const struct dsps_musb_wrapper *wrp = glue->wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct musb *musb = platform_get_drvdata(glue->musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) void __iomem *mbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (!musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dsps_dma_controller_resume(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) mbase = musb->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) musb_writel(mbase, wrp->control, glue->context.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) musb_writel(mbase, wrp->epintr_set, glue->context.epintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) musb_writel(mbase, wrp->mode, glue->context.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) musb->port_mode == MUSB_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dsps_mod_timer(glue, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static struct platform_driver dsps_usbss_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .probe = dsps_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .remove = dsps_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .name = "musb-dsps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .pm = &dsps_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .of_match_table = musb_dsps_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) module_platform_driver(dsps_usbss_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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