^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MUSB OTG driver DMA controller abstraction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005 Mentor Graphics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005-2006 by Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006-2007 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __MUSB_DMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __MUSB_DMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct musb_hw_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * DMA Controller Abstraction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * DMA Controllers are abstracted to allow use of a variety of different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * implementations of DMA, as allowed by the Inventra USB cores. On the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * host side, usbcore sets up the DMA mappings and flushes caches; on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * peripheral side, the gadget controller driver does. Responsibilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * of a DMA controller driver include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - Handling the details of moving multiple USB packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * in cooperation with the Inventra USB core, including especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * the correct RX side treatment of short packets and buffer-full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * states (both of which terminate transfers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - Knowing the correlation between dma channels and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Inventra core's local endpoint resources and data direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - Maintaining a list of allocated/available channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * - Updating channel status on interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * whether shared with the Inventra core or separate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MUSB_HSDMA_BASE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MUSB_HSDMA_CONTROL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MUSB_HSDMA_ADDRESS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MUSB_HSDMA_COUNT 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DMA_ADDR_INVALID (~(dma_addr_t)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_MUSB_PIO_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define is_dma_capable() (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define is_dma_capable() (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_USB_UX500_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define musb_dma_ux500(musb) (musb->ops->quirks & MUSB_DMA_UX500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define musb_dma_ux500(musb) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_USB_TI_CPPI41_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define musb_dma_cppi41(musb) (musb->ops->quirks & MUSB_DMA_CPPI41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define musb_dma_cppi41(musb) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #ifdef CONFIG_USB_TI_CPPI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define musb_dma_cppi(musb) (musb->ops->quirks & MUSB_DMA_CPPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define musb_dma_cppi(musb) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_USB_TUSB_OMAP_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define tusb_dma_omap(musb) (musb->ops->quirks & MUSB_DMA_TUSB_OMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define tusb_dma_omap(musb) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CONFIG_USB_INVENTRA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define musb_dma_inventra(musb) (musb->ops->quirks & MUSB_DMA_INVENTRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define musb_dma_inventra(musb) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define is_cppi_enabled(musb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (musb_dma_cppi(musb) || musb_dma_cppi41(musb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define is_cppi_enabled(musb) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * DMA channel status ... updated by the dma controller driver whenever that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * status changes, and protected by the overall controller spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum dma_channel_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* unallocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MUSB_DMA_STATUS_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* allocated ... but not busy, no errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MUSB_DMA_STATUS_FREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* busy ... transactions are active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MUSB_DMA_STATUS_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* transaction(s) aborted due to ... dma or memory bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MUSB_DMA_STATUS_BUS_ABORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* transaction(s) aborted due to ... core error or USB fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MUSB_DMA_STATUS_CORE_ABORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct dma_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * struct dma_channel - A DMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @private_data: channel-private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @max_len: the maximum number of bytes the channel can move in one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * transaction (typically representing many USB maximum-sized packets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @actual_len: how many bytes have been transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @status: current channel status (updated e.g. on interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * channels are associated with an endpoint for the duration of at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * one usb transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct dma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* FIXME not void* private_data, but a dma_controller * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) size_t max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) size_t actual_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum dma_channel_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bool desired_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bool rx_packet_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * dma_channel_status - return status of dma channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @c: the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Returns the software's view of the channel status. If that status is BUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * then it's possible that the hardware has completed (or aborted) a transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * so the driver needs to update that status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline enum dma_channel_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dma_channel_status(struct dma_channel *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * struct dma_controller - A DMA Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @musb: the usb controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @start: call this to start a DMA controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * return 0 on success, else negative errno
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @stop: call this to stop a DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * return 0 on success, else negative errno
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @channel_alloc: call this to allocate a DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @channel_release: call this to release a DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @channel_abort: call this to abort a pending DMA transaction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * returning it to FREE (but allocated) state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @dma_callback: invoked on DMA completion, useful to run platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * code such IRQ acknowledgment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Controllers manage dma channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct dma_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct musb *musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct dma_channel *(*channel_alloc)(struct dma_controller *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct musb_hw_ep *, u8 is_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void (*channel_release)(struct dma_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int (*channel_program)(struct dma_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u16 maxpacket, u8 mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dma_addr_t dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int (*channel_abort)(struct dma_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int (*is_compatible)(struct dma_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u16 maxpacket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void *buf, u32 length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void (*dma_callback)(struct dma_controller *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* called after channel_program(), may indicate a fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef CONFIG_MUSB_PIO_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) musb_dma_controller_create(struct musb *m, void __iomem *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline void musb_dma_controller_destroy(struct dma_controller *d) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) extern struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (*musb_dma_controller_create)(struct musb *, void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) extern void (*musb_dma_controller_destroy)(struct dma_controller *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Platform specific DMA functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) extern struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) musbhs_dma_controller_create(struct musb *musb, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) extern void musbhs_dma_controller_destroy(struct dma_controller *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) extern struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) extern irqreturn_t dma_controller_irq(int irq, void *private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) extern struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) tusb_dma_controller_create(struct musb *musb, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) extern void tusb_dma_controller_destroy(struct dma_controller *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) extern struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cppi_dma_controller_create(struct musb *musb, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) extern void cppi_dma_controller_destroy(struct dma_controller *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) extern struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cppi41_dma_controller_create(struct musb *musb, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) extern void cppi41_dma_controller_destroy(struct dma_controller *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) extern struct dma_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ux500_dma_controller_create(struct musb *musb, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) extern void ux500_dma_controller_destroy(struct dma_controller *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif /* __MUSB_DMA_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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