^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MUSB OTG driver debugfs support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Contact: Felipe Balbi <felipe.balbi@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "musb_debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct musb_register_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct musb_register_map musb_regmap[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { "FAddr", MUSB_FADDR, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { "Power", MUSB_POWER, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { "Frame", MUSB_FRAME, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { "Index", MUSB_INDEX, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { "Testmode", MUSB_TESTMODE, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { "TxMaxPp", MUSB_TXMAXP, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { "TxCSRp", MUSB_TXCSR, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { "RxMaxPp", MUSB_RXMAXP, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { "RxCSR", MUSB_RXCSR, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { "RxCount", MUSB_RXCOUNT, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { "IntrRxE", MUSB_INTRRXE, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { "IntrTxE", MUSB_INTRTXE, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { "IntrUsbE", MUSB_INTRUSBE, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { "DevCtl", MUSB_DEVCTL, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { "VControl", 0x68, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { "HWVers", 0x69, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { "LinkInfo", MUSB_LINKINFO, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { "VPLen", MUSB_VPLEN, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { "HS_EOF1", MUSB_HS_EOF1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { "FS_EOF1", MUSB_FS_EOF1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { "LS_EOF1", MUSB_LS_EOF1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "SOFT_RST", 0x7F, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { "DMA_CNTLch0", 0x204, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { "DMA_ADDRch0", 0x208, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { "DMA_COUNTch0", 0x20C, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { "DMA_CNTLch1", 0x214, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { "DMA_ADDRch1", 0x218, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { "DMA_COUNTch1", 0x21C, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { "DMA_CNTLch2", 0x224, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { "DMA_ADDRch2", 0x228, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { "DMA_COUNTch2", 0x22C, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { "DMA_CNTLch3", 0x234, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { "DMA_ADDRch3", 0x238, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { "DMA_COUNTch3", 0x23C, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { "DMA_CNTLch4", 0x244, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { "DMA_ADDRch4", 0x248, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { "DMA_COUNTch4", 0x24C, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { "DMA_CNTLch5", 0x254, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { "DMA_ADDRch5", 0x258, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { "DMA_COUNTch5", 0x25C, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { "DMA_CNTLch6", 0x264, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { "DMA_ADDRch6", 0x268, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { "DMA_COUNTch6", 0x26C, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { "DMA_CNTLch7", 0x274, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { "DMA_ADDRch7", 0x278, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { "DMA_COUNTch7", 0x27C, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { "ConfigData", MUSB_CONFIGDATA,8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { "BabbleCtl", MUSB_BABBLE_CTL,8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { "TxFIFOsz", MUSB_TXFIFOSZ, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { "RxFIFOsz", MUSB_RXFIFOSZ, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { "TxFIFOadd", MUSB_TXFIFOADD, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "RxFIFOadd", MUSB_RXFIFOADD, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { "EPInfo", MUSB_EPINFO, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { "RAMInfo", MUSB_RAMINFO, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { } /* Terminating Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int musb_regdump_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct musb *musb = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) seq_printf(s, "MUSB (M)HDRC Register Dump\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pm_runtime_get_sync(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) for (i = 0; i < ARRAY_SIZE(musb_regmap); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (musb_regmap[i].size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) seq_printf(s, "%-12s: %02x\n", musb_regmap[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) musb_readb(musb->mregs, musb_regmap[i].offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) seq_printf(s, "%-12s: %04x\n", musb_regmap[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) musb_readw(musb->mregs, musb_regmap[i].offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) seq_printf(s, "%-12s: %08x\n", musb_regmap[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) musb_readl(musb->mregs, musb_regmap[i].offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pm_runtime_mark_last_busy(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pm_runtime_put_autosuspend(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEFINE_SHOW_ATTRIBUTE(musb_regdump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int musb_test_mode_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct musb *musb = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pm_runtime_get_sync(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) test = musb_readb(musb->mregs, MUSB_TESTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pm_runtime_mark_last_busy(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pm_runtime_put_autosuspend(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (test == (MUSB_TEST_FORCE_HOST | MUSB_TEST_FORCE_FS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) seq_printf(s, "force host full-speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else if (test == (MUSB_TEST_FORCE_HOST | MUSB_TEST_FORCE_HS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) seq_printf(s, "force host high-speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else if (test == MUSB_TEST_FORCE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) seq_printf(s, "force host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else if (test == MUSB_TEST_FIFO_ACCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) seq_printf(s, "fifo access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else if (test == MUSB_TEST_FORCE_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) seq_printf(s, "force full-speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) else if (test == MUSB_TEST_FORCE_HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) seq_printf(s, "force high-speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else if (test == MUSB_TEST_PACKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) seq_printf(s, "test packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) else if (test == MUSB_TEST_K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) seq_printf(s, "test K\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else if (test == MUSB_TEST_J)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) seq_printf(s, "test J\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) else if (test == MUSB_TEST_SE0_NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) seq_printf(s, "test SE0 NAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int musb_test_mode_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return single_open(file, musb_test_mode_show, inode->i_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static ssize_t musb_test_mode_write(struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const char __user *ubuf, size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct seq_file *s = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct musb *musb = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) char buf[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) memset(buf, 0x00, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (copy_from_user(buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pm_runtime_get_sync(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) test = musb_readb(musb->mregs, MUSB_TESTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (test) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(musb->controller, "Error: test mode is already set. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "Please do USB Bus Reset to start a new test.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (strstarts(buf, "force host full-speed"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) test = MUSB_TEST_FORCE_HOST | MUSB_TEST_FORCE_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else if (strstarts(buf, "force host high-speed"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) test = MUSB_TEST_FORCE_HOST | MUSB_TEST_FORCE_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else if (strstarts(buf, "force host"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) test = MUSB_TEST_FORCE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else if (strstarts(buf, "fifo access"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) test = MUSB_TEST_FIFO_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else if (strstarts(buf, "force full-speed"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) test = MUSB_TEST_FORCE_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else if (strstarts(buf, "force high-speed"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) test = MUSB_TEST_FORCE_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else if (strstarts(buf, "test packet")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) test = MUSB_TEST_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) musb_load_testpacket(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else if (strstarts(buf, "test K"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) test = MUSB_TEST_K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else if (strstarts(buf, "test J"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) test = MUSB_TEST_J;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else if (strstarts(buf, "test SE0 NAK"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) test = MUSB_TEST_SE0_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) musb_writeb(musb->mregs, MUSB_TESTMODE, test);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pm_runtime_mark_last_busy(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pm_runtime_put_autosuspend(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct file_operations musb_test_mode_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .open = musb_test_mode_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .write = musb_test_mode_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .read = seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .llseek = seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .release = single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int musb_softconnect_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct musb *musb = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case OTG_STATE_A_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pm_runtime_get_sync(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reg = musb_readb(musb->mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) connect = reg & MUSB_DEVCTL_SESSION ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pm_runtime_mark_last_busy(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pm_runtime_put_autosuspend(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) connect = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) seq_printf(s, "%d\n", connect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int musb_softconnect_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return single_open(file, musb_softconnect_show, inode->i_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static ssize_t musb_softconnect_write(struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) const char __user *ubuf, size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct seq_file *s = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct musb *musb = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) char buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) memset(buf, 0x00, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pm_runtime_get_sync(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!strncmp(buf, "0", 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case OTG_STATE_A_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) musb_root_disconnect(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg = musb_readb(musb->mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) reg &= ~MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) musb_writeb(musb->mregs, MUSB_DEVCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) } else if (!strncmp(buf, "1", 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) switch (musb->xceiv->otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * musb_save_context() called in musb_runtime_suspend()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * might cache devctl with SESSION bit cleared during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * soft-disconnect, so specifically set SESSION bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * here to preserve it for musb_runtime_resume().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) musb->context.devctl |= MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) reg = musb_readb(musb->mregs, MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reg |= MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) musb_writeb(musb->mregs, MUSB_DEVCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pm_runtime_mark_last_busy(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pm_runtime_put_autosuspend(musb->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * In host mode, connect/disconnect the bus without physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * remove the devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct file_operations musb_softconnect_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .open = musb_softconnect_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .write = musb_softconnect_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .read = seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .llseek = seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .release = single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void musb_init_debugfs(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) root = debugfs_create_dir(dev_name(musb->controller), usb_debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) musb->debugfs_root = root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) debugfs_create_file("regdump", S_IRUGO, root, musb, &musb_regdump_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) debugfs_create_file("testmode", S_IRUGO | S_IWUSR, root, musb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) &musb_test_mode_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) debugfs_create_file("softconnect", S_IRUGO | S_IWUSR, root, musb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &musb_softconnect_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void /* __init_or_exit */ musb_exit_debugfs(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) debugfs_remove_recursive(musb->debugfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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