^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Min Guo <min.guo@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Yonglong Wu <yonglong.wu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/usb/role.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/usb/usb_phy_generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "musb_core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "musb_dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USB_L1INTS 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USB_L1INTM 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MTK_MUSB_TXFUNCADDR 0x0480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* MediaTek controller toggle enable and status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MUSB_RXTOG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MUSB_RXTOGEN 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MUSB_TXTOG 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MUSB_TXTOGEN 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MTK_TOGGLE_EN GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TX_INT_STATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RX_INT_STATUS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USBCOM_INT_STATUS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMA_INT_STATUS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMA_INTR_STATUS_MSK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMA_INTR_UNMASK_SET_MSK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct mtk_glue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct musb *musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct platform_device *musb_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct platform_device *usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct usb_phy *xceiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum phy_mode phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk *main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk *mcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk *univpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum usb_role role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct usb_role_switch *role_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int mtk_musb_clks_get(struct mtk_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct device *dev = glue->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) glue->main = devm_clk_get(dev, "main");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (IS_ERR(glue->main)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_err(dev, "fail to get main clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return PTR_ERR(glue->main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) glue->mcu = devm_clk_get(dev, "mcu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (IS_ERR(glue->mcu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dev_err(dev, "fail to get mcu clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return PTR_ERR(glue->mcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) glue->univpll = devm_clk_get(dev, "univpll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (IS_ERR(glue->univpll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(dev, "fail to get univpll clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return PTR_ERR(glue->univpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int mtk_musb_clks_enable(struct mtk_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = clk_prepare_enable(glue->main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_err(glue->dev, "failed to enable main clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) goto err_main_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = clk_prepare_enable(glue->mcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(glue->dev, "failed to enable mcu clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto err_mcu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = clk_prepare_enable(glue->univpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(glue->dev, "failed to enable univpll clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto err_univpll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err_univpll_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk_disable_unprepare(glue->mcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) err_mcu_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk_disable_unprepare(glue->main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) err_main_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void mtk_musb_clks_disable(struct mtk_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk_disable_unprepare(glue->univpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clk_disable_unprepare(glue->mcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_disable_unprepare(glue->main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int mtk_otg_switch_set(struct mtk_glue *glue, enum usb_role role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct musb *musb = glue->musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 devctl = readb(musb->mregs + MUSB_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum usb_role new_role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (role == glue->role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) switch (role) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case USB_ROLE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) glue->phy_mode = PHY_MODE_USB_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) new_role = USB_ROLE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (glue->role == USB_ROLE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) phy_power_on(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) devctl |= MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MUSB_HST_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case USB_ROLE_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) musb->xceiv->otg->state = OTG_STATE_B_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) glue->phy_mode = PHY_MODE_USB_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) new_role = USB_ROLE_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) devctl &= ~MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (glue->role == USB_ROLE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) phy_power_on(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUSB_DEV_MODE(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case USB_ROLE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) glue->phy_mode = PHY_MODE_USB_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) new_role = USB_ROLE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) devctl &= ~MUSB_DEVCTL_SESSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (glue->role != USB_ROLE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) phy_power_off(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(glue->dev, "Invalid State\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) glue->role = new_role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) phy_set_mode(glue->phy, glue->phy_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int musb_usb_role_sx_set(struct usb_role_switch *sw, enum usb_role role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return mtk_otg_switch_set(usb_role_switch_get_drvdata(sw), role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static enum usb_role musb_usb_role_sx_get(struct usb_role_switch *sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct mtk_glue *glue = usb_role_switch_get_drvdata(sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return glue->role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int mtk_otg_switch_init(struct mtk_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct usb_role_switch_desc role_sx_desc = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) role_sx_desc.set = musb_usb_role_sx_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) role_sx_desc.get = musb_usb_role_sx_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) role_sx_desc.fwnode = dev_fwnode(glue->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) role_sx_desc.driver_data = glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) glue->role_sw = usb_role_switch_register(glue->dev, &role_sx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return PTR_ERR_OR_ZERO(glue->role_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void mtk_otg_switch_exit(struct mtk_glue *glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return usb_role_switch_unregister(glue->role_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static irqreturn_t generic_interrupt(int irq, void *__hci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct musb *musb = __hci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) spin_lock_irqsave(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) musb->int_usb = musb_clearb(musb->mregs, MUSB_INTRUSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) musb->int_rx = musb_clearw(musb->mregs, MUSB_INTRRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) musb->int_tx = musb_clearw(musb->mregs, MUSB_INTRTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* ep0 FADDR must be 0 when (re)entering peripheral mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) musb_ep_select(musb->mregs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) musb_writeb(musb->mregs, MUSB_FADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (musb->int_usb || musb->int_tx || musb->int_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) retval = musb_interrupt(musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spin_unlock_irqrestore(&musb->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static irqreturn_t mtk_musb_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct musb *musb = (struct musb *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 l1_ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) l1_ints = musb_readl(musb->mregs, USB_L1INTS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) musb_readl(musb->mregs, USB_L1INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (l1_ints & (TX_INT_STATUS | RX_INT_STATUS | USBCOM_INT_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) retval = generic_interrupt(irq, musb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #if defined(CONFIG_USB_INVENTRA_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (l1_ints & DMA_INT_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) retval = dma_controller_irq(irq, musb->dma_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static u32 mtk_musb_busctl_offset(u8 epnum, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return MTK_MUSB_TXFUNCADDR + offset + 8 * epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static u8 mtk_musb_clearb(void __iomem *addr, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* W1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) data = musb_readb(addr, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) musb_writeb(addr, offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static u16 mtk_musb_clearw(void __iomem *addr, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* W1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) data = musb_readw(addr, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) musb_writew(addr, offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int mtk_musb_set_mode(struct musb *musb, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct mtk_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) enum phy_mode new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enum usb_role new_role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case MUSB_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) new_mode = PHY_MODE_USB_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) new_role = USB_ROLE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case MUSB_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) new_mode = PHY_MODE_USB_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) new_role = USB_ROLE_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case MUSB_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) new_mode = PHY_MODE_USB_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) new_role = USB_ROLE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(glue->dev, "Invalid mode request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (glue->phy_mode == new_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (musb->port_mode != MUSB_OTG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(glue->dev, "Does not support changing modes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mtk_otg_switch_set(glue, new_role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int mtk_musb_init(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct mtk_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) glue->musb = musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) musb->phy = glue->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) musb->xceiv = glue->xceiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) musb->is_host = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) musb->isr = mtk_musb_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Set TX/RX toggle enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) musb_writew(musb->mregs, MUSB_TXTOGEN, MTK_TOGGLE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) musb_writew(musb->mregs, MUSB_RXTOGEN, MTK_TOGGLE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (musb->port_mode == MUSB_OTG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = mtk_otg_switch_init(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = phy_init(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goto err_phy_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = phy_power_on(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) goto err_phy_power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) phy_set_mode(glue->phy, glue->phy_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #if defined(CONFIG_USB_INVENTRA_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) musb_writel(musb->mregs, MUSB_HSDMA_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DMA_INTR_STATUS_MSK | DMA_INTR_UNMASK_SET_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) musb_writel(musb->mregs, USB_L1INTM, TX_INT_STATUS | RX_INT_STATUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) USBCOM_INT_STATUS | DMA_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) err_phy_power_on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) phy_exit(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) err_phy_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mtk_otg_switch_exit(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static u16 mtk_musb_get_toggle(struct musb_qh *qh, int is_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct musb *musb = qh->hw_ep->musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 epnum = qh->hw_ep->epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u16 toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) toggle = musb_readw(musb->mregs, is_out ? MUSB_TXTOG : MUSB_RXTOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return toggle & (1 << epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static u16 mtk_musb_set_toggle(struct musb_qh *qh, int is_out, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct musb *musb = qh->hw_ep->musb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 epnum = qh->hw_ep->epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u16 value, toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) toggle = usb_gettoggle(urb->dev, qh->epnum, is_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (is_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) value = musb_readw(musb->mregs, MUSB_TXTOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) value |= toggle << epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) musb_writew(musb->mregs, MUSB_TXTOG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) value = musb_readw(musb->mregs, MUSB_RXTOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) value |= toggle << epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) musb_writew(musb->mregs, MUSB_RXTOG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int mtk_musb_exit(struct musb *musb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct device *dev = musb->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct mtk_glue *glue = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mtk_otg_switch_exit(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) phy_power_off(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) phy_exit(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mtk_musb_clks_disable(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct musb_platform_ops mtk_musb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .quirks = MUSB_DMA_INVENTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .init = mtk_musb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .get_toggle = mtk_musb_get_toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .set_toggle = mtk_musb_set_toggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .exit = mtk_musb_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #ifdef CONFIG_USB_INVENTRA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .dma_init = musbhs_dma_controller_create_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .dma_exit = musbhs_dma_controller_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .clearb = mtk_musb_clearb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .clearw = mtk_musb_clearw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .busctl_offset = mtk_musb_busctl_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .set_mode = mtk_musb_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MTK_MUSB_MAX_EP_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MTK_MUSB_RAM_BITS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct musb_fifo_cfg mtk_musb_mode_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 1024, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 1024, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct musb_hdrc_config mtk_musb_hdrc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .fifo_cfg = mtk_musb_mode_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .fifo_cfg_size = ARRAY_SIZE(mtk_musb_mode_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .multipoint = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .dyn_fifo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .num_eps = MTK_MUSB_MAX_EP_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .ram_bits = MTK_MUSB_RAM_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct platform_device_info mtk_dev_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .name = "musb-hdrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .id = PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int mtk_musb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct musb_hdrc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct mtk_glue *glue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct platform_device_info pinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!glue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) glue->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = of_platform_populate(np, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(dev, "failed to create child devices at %p\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = mtk_musb_clks_get(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pdata->config = &mtk_musb_hdrc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pdata->platform_ops = &mtk_musb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pdata->mode = usb_get_dr_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (IS_ENABLED(CONFIG_USB_MUSB_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pdata->mode = USB_DR_MODE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) else if (IS_ENABLED(CONFIG_USB_MUSB_GADGET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pdata->mode = USB_DR_MODE_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) switch (pdata->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) glue->phy_mode = PHY_MODE_USB_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) glue->role = USB_ROLE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) glue->phy_mode = PHY_MODE_USB_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) glue->role = USB_ROLE_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case USB_DR_MODE_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) glue->phy_mode = PHY_MODE_USB_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) glue->role = USB_ROLE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(&pdev->dev, "Error 'dr_mode' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) glue->phy = devm_of_phy_get_by_index(dev, np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_ERR(glue->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(dev, "fail to getting phy %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PTR_ERR(glue->phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return PTR_ERR(glue->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) glue->usb_phy = usb_phy_generic_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (IS_ERR(glue->usb_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(dev, "fail to registering usb-phy %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PTR_ERR(glue->usb_phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return PTR_ERR(glue->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) glue->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (IS_ERR(glue->xceiv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = PTR_ERR(glue->xceiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(dev, "fail to getting usb-phy %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto err_unregister_usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) platform_set_drvdata(pdev, glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = mtk_musb_clks_enable(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto err_enable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pinfo = mtk_dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pinfo.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pinfo.res = pdev->resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pinfo.num_res = pdev->num_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pinfo.data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pinfo.size_data = sizeof(*pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) glue->musb_pdev = platform_device_register_full(&pinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (IS_ERR(glue->musb_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = PTR_ERR(glue->musb_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_err(dev, "failed to register musb device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) goto err_device_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) err_device_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mtk_musb_clks_disable(glue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) err_enable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) err_unregister_usb_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) usb_phy_generic_unregister(glue->usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int mtk_musb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct mtk_glue *glue = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct platform_device *usb_phy = glue->usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) platform_device_unregister(glue->musb_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) usb_phy_generic_unregister(usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const struct of_device_id mtk_musb_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {.compatible = "mediatek,mtk-musb",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MODULE_DEVICE_TABLE(of, mtk_musb_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static struct platform_driver mtk_musb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .probe = mtk_musb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .remove = mtk_musb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .name = "musb-mtk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .of_match_table = of_match_ptr(mtk_musb_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) module_platform_driver(mtk_musb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MODULE_DESCRIPTION("MediaTek MUSB Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MODULE_AUTHOR("Min Guo <min.guo@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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